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integration/soc: expose integrated_rom_mode to allow ROM to be writable (useful for BIOS/ROM development where content is reloaded over UARTBone/Etherbone).

This commit is contained in:
Florent Kermarrec 2020-08-24 18:19:03 +02:00
parent 885c339d97
commit 4364043b08
2 changed files with 8 additions and 7 deletions
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4
litex/soc/integration/soc.py
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@ -803,8 +803,8 @@ class SoC(Module):
self.bus.regions[name])) self.bus.regions[name]))
setattr(self.submodules, name, ram) setattr(self.submodules, name, ram)
def add_rom(self, name, origin, size, contents=[]): def add_rom(self, name, origin, size, contents=[], mode="r"):
self.add_ram(name, origin, size, contents, mode="r") self.add_ram(name, origin, size, contents, mode=mode)
def add_csr_bridge(self, origin, register=False): def add_csr_bridge(self, origin, register=False):
csr_bridge_cls = { csr_bridge_cls = {

3
litex/soc/integration/soc_core.py
View File

@ -71,6 +71,7 @@ class SoCCore(LiteXSoC):
cpu_cls = None, cpu_cls = None,
# ROM parameters # ROM parameters
integrated_rom_size = 0, integrated_rom_size = 0,
integrated_rom_mode = "r",
integrated_rom_init = [], integrated_rom_init = [],
# SRAM parameters # SRAM parameters
integrated_sram_size = 0x2000, integrated_sram_size = 0x2000,
@ -161,7 +162,7 @@ class SoCCore(LiteXSoC):
# Add integrated ROM # Add integrated ROM
if integrated_rom_size: if integrated_rom_size:
self.add_rom("rom", self.cpu.reset_address, integrated_rom_size, integrated_rom_init) self.add_rom("rom", self.cpu.reset_address, integrated_rom_size, integrated_rom_init, integrated_rom_mode)
# Add integrated SRAM # Add integrated SRAM
if integrated_sram_size: if integrated_sram_size: