integration/soc: expose integrated_rom_mode to allow ROM to be writable (useful for BIOS/ROM development where content is reloaded over UARTBone/Etherbone).
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@ -803,8 +803,8 @@ class SoC(Module):
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self.bus.regions[name]))
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self.bus.regions[name]))
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setattr(self.submodules, name, ram)
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setattr(self.submodules, name, ram)
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def add_rom(self, name, origin, size, contents=[]):
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def add_rom(self, name, origin, size, contents=[], mode="r"):
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self.add_ram(name, origin, size, contents, mode="r")
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self.add_ram(name, origin, size, contents, mode=mode)
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def add_csr_bridge(self, origin, register=False):
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def add_csr_bridge(self, origin, register=False):
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csr_bridge_cls = {
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csr_bridge_cls = {
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@ -1170,10 +1170,10 @@ class LiteXSoC(SoC):
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if spd_byte < len(module._spd_data):
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if spd_byte < len(module._spd_data):
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mem[i] |= module._spd_data[spd_byte]
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mem[i] |= module._spd_data[spd_byte]
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self.add_rom(
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self.add_rom(
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name="spd",
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name = "spd",
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origin=self.mem_map.get("spd", None),
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origin = self.mem_map.get("spd", None),
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size=len(module._spd_data),
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size = len(module._spd_data),
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contents=mem,
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contents = mem,
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)
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)
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if not with_soc_interconnect: return
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if not with_soc_interconnect: return
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@ -71,6 +71,7 @@ class SoCCore(LiteXSoC):
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cpu_cls = None,
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cpu_cls = None,
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# ROM parameters
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# ROM parameters
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integrated_rom_size = 0,
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integrated_rom_size = 0,
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integrated_rom_mode = "r",
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integrated_rom_init = [],
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integrated_rom_init = [],
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# SRAM parameters
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# SRAM parameters
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integrated_sram_size = 0x2000,
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integrated_sram_size = 0x2000,
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@ -161,7 +162,7 @@ class SoCCore(LiteXSoC):
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# Add integrated ROM
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# Add integrated ROM
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if integrated_rom_size:
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if integrated_rom_size:
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self.add_rom("rom", self.cpu.reset_address, integrated_rom_size, integrated_rom_init)
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self.add_rom("rom", self.cpu.reset_address, integrated_rom_size, integrated_rom_init, integrated_rom_mode)
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# Add integrated SRAM
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# Add integrated SRAM
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if integrated_sram_size:
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if integrated_sram_size:
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