corelogic: reorder buffer (untested)
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43653dbe1a
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@ -0,0 +1,80 @@
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from migen.fhdl.structure import *
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class ReorderSlot:
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def __init__(self, tag_width, data_width):
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self.wait_data = Signal()
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self.has_data = Signal()
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self.tag = Signal(BV(tag_width))
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self.data = Signal(BV(data_width))
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class ReorderBuffer:
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def __init__(self, tag_width, data_width, depth):
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self.depth = depth
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# issue
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self.can_issue = Signal()
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self.issue = Signal()
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self.tag_issue = Signal(BV(tag_width))
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# call
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self.call = Signal()
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self.tag_call = Signal(BV(tag_width))
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self.data_call = Signal(BV(data_width))
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# readback
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self.can_read = Signal()
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self.read = Signal()
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self.data_read = Signal(BV(data_width))
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self._empty_count = Signal(BV(bits_for(self.depth)), reset=self.depth)
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self._produce = Signal(BV(bits_for(self.depth-1)))
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self._consume = Signal(BV(bits_for(self.depth-1)))
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self._slots = Array(ReorderSlot(tag_width, data_width)
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for n in range(self.depth))
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def get_fragment(self):
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# issue
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comb = [
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self.can_issue.eq(self._empty_count != 0)
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]
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sync = [
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If(self.issue & self.can_issue,
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self._empty_count.eq(self._empty_count - 1),
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If(self._produce == self.depth - 1,
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self._produce.eq(0)
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).Else(
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self._produce.eq(self._produce + 1)
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),
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self._slots[self._produce].wait_data.eq(1),
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self._slots[self._produce].tag.eq(self.tag_issue)
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)
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]
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# call
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for n, slot in enumerate(self._slots):
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sync.append(
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If(self.call & slot.wait_data & (self.tag_call == slot.tag),
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slot.wait_data.eq(0),
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slot.has_data.eq(1),
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slot.data.eq(self.data_call)
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)
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)
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# readback
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comb += [
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self.can_read.eq(self._slots[self._consume].has_data),
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self.data_read.eq(self._slots[self._consume].data)
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]
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sync += [
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If(self.read & self.can_read,
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self._empty_count.eq(self._empty_count + 1),
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If(self._consume == self.depth - 1,
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self._consume.eq(0)
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).Else(
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self._consume.eq(self._consume + 1)
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),
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self._slots[self._consume].has_data.eq(0)
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)
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]
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return Fragment(comb, sync)
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