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crg: support for resetless system clock domain

This commit is contained in:
Sebastien Bourdeauducq 2013-05-07 19:09:56 +02:00
parent 6a4c194aab
commit 439f032921
2 changed files with 15 additions and 11 deletions
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10
mibuild/crg.py
View File

@ -3,11 +3,13 @@ from migen.fhdl.module import Module
class SimpleCRG(Module):
def __init__(self, platform, clk_name, rst_name, rst_invert=False):
reset_less = rst_name is None
self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
self._clk = platform.request(clk_name)
self._rst = platform.request(rst_name)
self.clock_domains.cd_sys = ClockDomain()
self.comb += self.cd_sys.clk.eq(self._clk)
if not reset_less:
if rst_invert:
self.comb += self.cd_sys.rst.eq(~self._rst)
self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
else:
self.comb += self.cd_sys.rst.eq(self._rst)
self.comb += self.cd_sys.rst.eq(platform.request(rst_name))

12
mibuild/xilinx_ise.py
View File

@ -21,18 +21,20 @@ class CRG_SE(SimpleCRG):
class CRG_DS(Module):
def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
self.clock_domains.cd_sys = ClockDomain()
reset_less = rst_name is None
self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
self._clk = platform.request(clk_name)
if rst_invert:
self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
else:
self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
_add_period_constraint(platform, self._clk.p, period)
self.specials += Instance("IBUFGDS",
Instance.Input("I", self._clk.p),
Instance.Input("IB", self._clk.n),
Instance.Output("O", self.cd_sys.clk)
)
if not reset_less:
if rst_invert:
self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
else:
self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
def _format_constraint(c):
if isinstance(c, Pins):