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Remove undriven reset signals

This commit is contained in:
Sebastien Bourdeauducq 2013-04-25 20:19:49 +02:00
parent de76faf757
commit 43ac5c8471
2 changed files with 3 additions and 3 deletions
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4
milkymist/dvisampler/clocking.py
View File

@ -13,8 +13,8 @@ class Clocking(Module, AutoCSR):
self.serdesstrobe = Signal() self.serdesstrobe = Signal()
self.clock_domains._cd_pix = ClockDomain() self.clock_domains._cd_pix = ClockDomain()
self.clock_domains._cd_pix5x = ClockDomain() self.clock_domains._cd_pix5x = ClockDomain()
self.clock_domains._cd_pix10x = ClockDomain() self.clock_domains._cd_pix10x = ClockDomain(reset_less=True)
self.clock_domains._cd_pix20x = ClockDomain() self.clock_domains._cd_pix20x = ClockDomain(reset_less=True)
### ###

2
milkymist/m1crg/__init__.py
View File

@ -13,7 +13,7 @@ class M1CRG(Module, AutoCSR):
self.clock_domains.cd_sys4x_rd = ClockDomain() self.clock_domains.cd_sys4x_rd = ClockDomain()
self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain()
self.clock_domains.cd_vga = ClockDomain() self.clock_domains.cd_vga = ClockDomain(reset_less=True)
self.clk4x_wr_strb = Signal() self.clk4x_wr_strb = Signal()
self.clk4x_rd_strb = Signal() self.clk4x_rd_strb = Signal()