build/generic_platform: replace set with list for sources/verilog_include_paths

Python does not have native OrderedSet and we need to be able to preserve the order of the sources
for some backends (Verilator for instance), so use list instead of set.

litex/build/generic_platform.py

@@ -1,5 +1,5 @@
 # This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
-# This file is Copyright (c) 2014-2018 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
 # This file is Copyright (c) 2015 Yann Sionneau <ys@m-labs.hk>
 # License: BSD
 
@@ -266,8 +266,8 @@ class GenericPlatform:
         if name is None:
             name = self.__module__.split(".")[-1]
         self.name = name
-        self.sources = set()
-        self.verilog_include_paths = set()
+        self.sources = []
+        self.verilog_include_paths = []
         self.finalized = False
 
     def request(self, *args, **kwargs):
@@ -325,7 +325,7 @@ class GenericPlatform:
         if library is None:
             library = "work"
 
-        self.sources.add((os.path.abspath(filename), language, library))
+        self.sources.append((os.path.abspath(filename), language, library))
 
     def add_sources(self, path, *filenames, language=None, library=None):
         for f in filenames:
@@ -349,7 +349,7 @@ class GenericPlatform:
                 self.add_source(filename, _language, library)
 
     def add_verilog_include_path(self, path):
-        self.verilog_include_paths.add(os.path.abspath(path))
+        self.verilog_include_paths.append(os.path.abspath(path))
 
     def resolve_signals(self, vns):
         # resolve signal names in constraints