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build/generic_platform: replace set with list for sources/verilog_include_paths 

Python does not have native OrderedSet and we need to be able to preserve the order of the sources
for some backends (Verilator for instance), so use list instead of set.
This commit is contained in:
Florent Kermarrec 2019-10-17 09:52:31 +02:00
parent 97a77b950c
commit 43f5d1ef13
1 changed files with 5 additions and 5 deletions
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10
litex/build/generic_platform.py
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@ -1,5 +1,5 @@
# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk> # This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
# This file is Copyright (c) 2014-2018 Florent Kermarrec <florent@enjoy-digital.fr> # This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2015 Yann Sionneau <ys@m-labs.hk> # This file is Copyright (c) 2015 Yann Sionneau <ys@m-labs.hk>
# License: BSD # License: BSD
@ -266,8 +266,8 @@ class GenericPlatform:
if name is None: if name is None:
name = self.__module__.split(".")[-1] name = self.__module__.split(".")[-1]
self.name = name self.name = name
self.sources = set() self.sources = []
self.verilog_include_paths = set() self.verilog_include_paths = []
self.finalized = False self.finalized = False
def request(self, *args, **kwargs): def request(self, *args, **kwargs):
@ -325,7 +325,7 @@ class GenericPlatform:
if library is None: if library is None:
library = "work" library = "work"
self.sources.add((os.path.abspath(filename), language, library)) self.sources.append((os.path.abspath(filename), language, library))
def add_sources(self, path, *filenames, language=None, library=None): def add_sources(self, path, *filenames, language=None, library=None):
for f in filenames: for f in filenames:
@ -349,7 +349,7 @@ class GenericPlatform:
self.add_source(filename, _language, library) self.add_source(filename, _language, library)
def add_verilog_include_path(self, path): def add_verilog_include_path(self, path):
self.verilog_include_paths.add(os.path.abspath(path)) self.verilog_include_paths.append(os.path.abspath(path))
def resolve_signals(self, vns): def resolve_signals(self, vns):
# resolve signal names in constraints # resolve signal names in constraints