mac: change default interface (core)

This commit is contained in:
Florent Kermarrec 2015-01-28 20:55:18 +01:00
parent fb00202427
commit 44113d754f

View file

@ -3,20 +3,20 @@ from liteeth.mac.core import LiteEthMACCore
from liteeth.mac.frontend import wishbone from liteeth.mac.frontend import wishbone
class LiteEthMAC(Module, AutoCSR): class LiteEthMAC(Module, AutoCSR):
def __init__(self, phy, dw, interface="wishbone", endianness="be", def __init__(self, phy, dw, interface="core", endianness="be",
with_hw_preamble_crc=True): with_hw_preamble_crc=True):
self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_hw_preamble_crc) self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_hw_preamble_crc)
self.csrs = None self.csrs = None
if interface == "wishbone": if interface == "core":
self.sink, self.source = self.core.sink, self.core.source
elif interface == "wishbone":
self.interface = wishbone.LiteEthMACWishboneInterface(dw, 2, 2) self.interface = wishbone.LiteEthMACWishboneInterface(dw, 2, 2)
self.ev, self.bus = self.interface.sram.ev, self.interface.bus self.ev, self.bus = self.interface.sram.ev, self.interface.bus
self.csrs = self.interface.get_csrs() self.csrs = self.interface.get_csrs()
elif interface == "dma": elif interface == "dma":
raise NotImplementedError raise NotImplementedError
elif interface == "core":
self.sink, self.source = self.core.sink, self.core.source
else: else:
raise ValueError("EthMAC only supports Wishbone, DMA or core interfaces") raise ValueError(inteface + " not supported by LiteEthMac!")
def get_csrs(self): def get_csrs(self):
return self.csrs return self.csrs