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soc/integration/soc_core: add integrated_sram_init

This commit is contained in:
Florent Kermarrec 2019-04-25 17:30:03 +02:00
parent f27084c6c0
commit 4443b5075b
1 changed files with 2 additions and 2 deletions
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4
litex/soc/integration/soc_core.py
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@ -143,7 +143,7 @@ class SoCCore(Module):
def __init__(self, platform, clk_freq, def __init__(self, platform, clk_freq,
cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None, cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
integrated_rom_size=0, integrated_rom_init=[], integrated_rom_size=0, integrated_rom_init=[],
integrated_sram_size=4096, integrated_sram_size=4096, integrated_sram_init=[],
integrated_main_ram_size=0, integrated_main_ram_init=[], integrated_main_ram_size=0, integrated_main_ram_init=[],
shadow_base=0x80000000, shadow_base=0x80000000,
csr_data_width=8, csr_address_width=14, csr_expose=False, csr_data_width=8, csr_address_width=14, csr_expose=False,
@ -223,7 +223,7 @@ class SoCCore(Module):
self.register_rom(self.rom.bus, integrated_rom_size) self.register_rom(self.rom.bus, integrated_rom_size)
if integrated_sram_size: if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size) self.submodules.sram = wishbone.SRAM(integrated_sram_size, init=integrated_sram_init)
self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size) self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size)
# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping. # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.