simplify code and use Sink/Source instead of records
This commit is contained in:
Florent Kermarrec
parent
6f7d85b95c
commit
4472dac603
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@ -1,14 +1,9 @@
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from migen.fhdl.std import *
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from migen.genlib.record import *
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.misc import chooser
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from migen.bank.description import *
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from litescope.common import *
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from migen.bus import wishbone
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from migen.genlib.misc import chooser
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from misoclib.uart import UARTRX, UARTTX
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from litescope.common import *
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class UART(Module, AutoCSR):
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def __init__(self, pads, clk_freq, baud=115200):
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self._tuning_word = CSRStorage(32, reset=int((baud/clk_freq)*2**32))
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@ -1,16 +1,16 @@
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from migen.genlib.record import *
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fsm import FSM, NextState
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from migen.flow.actor import *
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from migen.actorlib.fifo import AsyncFIFO, SyncFIFO
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from migen.flow.plumbing import Buffer
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from migen.fhdl.specials import Memory
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def dat_layout(dw):
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return [
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("stb", 1, DIR_M_TO_S),
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("dat", dw, DIR_M_TO_S)
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]
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def data_layout(dw):
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return [("data", dw, DIR_M_TO_S)]
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def hit_layout():
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return [
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("stb", 1, DIR_M_TO_S),
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("hit", 1, DIR_M_TO_S)
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]
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return [("hit", 1, DIR_M_TO_S)]
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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@ -0,0 +1,94 @@
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from litescope.common import *
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class LiteScopeTerm(Module):
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def __init__(self, dw):
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self.dw = dw
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self.sink = sink = Sink(data_layout(dw))
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self.source = source = Source(hit_layout())
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self.trig = Signal(dw)
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self.mask = Signal(dw)
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###
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self.comb += [
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source.stb.eq(sink.stb),
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source.hit.eq((sink.data & self.mask) == self.trig),
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sink.ack.eq(source.ack)
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]
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class LiteScopeTermCSR(LiteScopeTerm, AutoCSR):
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def __init__(self, dw):
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LiteScopeTerm.__init__(self, dw)
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self._trig = CSRStorage(dw)
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self._mask = CSRStorage(dw)
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###
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self.comb += [
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self.trig.eq(self._trig.storage),
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self.mask.eq(self._mask.storage)
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]
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class LiteScopeRangeDetector(Module):
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def __init__(self, dw):
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self.dw = dw
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self.sink = sink = Sink(data_layout(dw))
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self.source = source = Source(hit_layout())
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self.low = Signal(dw)
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self.high = Signal(dw)
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###
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self.comb += [
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source.stb.eq(sink.stb),
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source.hit.eq((sink.data >= self.low) & (sink.data <= self.high)),
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sink.ack.eq(source.ack)
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]
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class LiteScopeRangeDetectorCSR(LiteScopeRangeDetector, AutoCSR):
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def __init__(self, dw):
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LiteScopeRangeDetector.__init__(self, dw)
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self._low = CSRStorage(dw)
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self._high = CSRStorage(dw)
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###
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self.comb += [
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self.low.eq(self._low.storage),
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self.high.eq(self._high.storage)
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]
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class LiteScopeEdgeDetector(Module):
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def __init__(self, dw):
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self.dw = dw
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self.sink = sink = Sink(data_layout(dw))
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self.source = source = Source(hit_layout())
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self.rising_mask = Signal(dw)
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self.falling_mask = Signal(dw)
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self.both_mask = Signal(dw)
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###
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self.buffer = Buffer(self.sink.description)
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self.comb += Record.connect(self.sink, self.buffer.sink)
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rising = Signal(dw)
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rising.eq(self.rising_mask & sink.data & ~self.buffer.source.data)
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falling = Signal(dw)
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falling.eq(self.falling_mask & sink.data & ~self.buffer.source.data)
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both = Signal(dw)
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both.eq(self.both_mask & sink.data & ~self.buffer.source.data)
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self.comb += [
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source.stb.eq(sink.stb & self.buffer.source.stb),
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self.buffer.source.ack.eq(source.ack),
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source.hit.eq(rising | falling | both)
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]
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class LiteScopeEdgeDetectorCSR(LiteScopeEdgeDetector, AutoCSR):
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def __init__(self, dw):
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LiteScopeEdgeDetector.__init__(self, dw)
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self._rising = CSRStorage(dw)
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self._falling = CSRStorage(dw)
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self._both = CSRStorage(dw)
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###
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self.comb += [
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self.rising.eq(self._rising.storage),
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self.falling.eq(self._falling.storage),
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self.both.eq(self._both.storage)
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]
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@ -1,27 +1,17 @@
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFOBuffered as SyncFIFO
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.record import *
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from litescope.common import *
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class LiteScopeRunLengthEncoder(Module, AutoCSR):
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def __init__(self, width, length=1024):
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self.width = width
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class LiteScopeRunLengthEncoder(Module):
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def __init__(self, dw, length=1024):
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self.dw = dw
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self.length = length
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self.sink = Record(dat_layout(width))
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self.source = Record(dat_layout(width))
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self._enable = CSRStorage()
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self.sink = sink = Sink(data_layout(dw))
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self.source = source = Source(data_layout(dw))
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self.enable = Signal()
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###
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enable = self._enable.storage
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sink_d = Record(dat_layout(width))
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self.sync += If(self.sink.stb, sink_d.eq(self.sink))
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sink_d = Sink(data_layout(dw))
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self.sync += If(sink.stb, sink_d.eq(sink))
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cnt = Signal(max=length)
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cnt_inc = Signal()
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@ -37,78 +27,79 @@ class LiteScopeRunLengthEncoder(Module, AutoCSR):
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self.comb += cnt_max.eq(cnt == length)
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change = Signal()
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self.comb += change.eq(self.sink.stb & (self.sink.dat != sink_d.dat))
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self.comb += change.eq(sink.stb & (sink.dat != sink_d.dat))
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fsm = FSM(reset_state="BYPASS")
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self.submodules += fsm
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fsm.act("BYPASS",
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sink_d.connect(self.source),
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Record.connect(sink_d, source),
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cnt_reset.eq(1),
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If(enable & ~change & self.sink.stb, NextState("COUNT"))
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If(self.enable & ~change & sink.stb, NextState("COUNT"))
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)
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fsm.act("COUNT",
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cnt_inc.eq(self.sink.stb),
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If(change | cnt_max | ~enable,
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self.source.stb.eq(1),
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self.source.dat[width-1].eq(1), # Set RLE bit
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self.source.dat[:flen(cnt)].eq(cnt),
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cnt_inc.eq(sink.stb),
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If(change | cnt_max | ~self.enable,
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source.stb.eq(1),
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source.dat[dw-1].eq(1), # Set RLE bit
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source.dat[:flen(cnt)].eq(cnt),
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NextState("BYPASS")
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)
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),
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)
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class LiteScopeRunLengthEncoderCSR(Module, AutoCSR):
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def __init__(self, rle):
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self.submodules += rle
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self._enable = CSRStorage()
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###
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self.comb += rle.enable.eq(self_enable.storage)
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class LiteScopeRecorder(Module, AutoCSR):
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def __init__(self, width, depth):
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self.width = width
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def __init__(self, dw, depth):
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self.dw = dw
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self.trig_sink = Record(hit_layout())
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self.dat_sink = Record(dat_layout(width))
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self.trigger_sink = trigger_sink = Sink(hit_layout())
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self.data_sink = data_sink = Sink(data_layout(dw))
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self._trigger = CSR()
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self._length = CSRStorage(bits_for(depth))
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self._offset = CSRStorage(bits_for(depth))
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self._done = CSRStatus()
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self._read_en = CSR()
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self._read_empty = CSRStatus()
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self._read_dat = CSRStatus(width)
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self._source_stb = CSRStatus()
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self._source_ack = CSR()
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self._source_data = CSRStatus(dw)
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###
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fifo = InsertReset(SyncFIFO(width, depth))
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fifo = InsertReset(SyncFIFO(data_layout(dw), depth, buffered=True))
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self.submodules += fifo
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.comb += [
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self._read_empty.status.eq(~fifo.readable),
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self._read_dat.status.eq(fifo.dout),
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self._source_stb.status.eq(fifo.source.stb),
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self._source_data.status.eq(fifo.source.data)
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]
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fsm.act("IDLE",
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If(self._trigger.re & self._trigger.r,
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self._done.status.eq(1),
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If(self._trigger.re,
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NextState("PRE_HIT_RECORDING"),
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fifo.reset.eq(1),
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),
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fifo.re.eq(self._read_en.re & self._read_en.r),
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self._done.status.eq(1)
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fifo.source.ack.eq(self._source_ack.re)
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)
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fsm.act("PRE_HIT_RECORDING",
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fifo.we.eq(self.dat_sink.stb),
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fifo.din.eq(self.dat_sink.dat),
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fifo.sink.stb.eq(data_sink.stb),
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fifo.sink.data.eq(data_sink.data),
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data_sink.ack.eq(fifo.sink.ack),
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fifo.re.eq(fifo.level >= self._offset.storage),
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If(self.trig_sink.stb & self.trig_sink.hit, NextState("POST_HIT_RECORDING"))
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fifo.source.ack.eq(fifo.fifo.level >= self._offset.storage),
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If(trigger_sink.stb & trigger_sink.hit, NextState("POST_HIT_RECORDING"))
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)
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fsm.act("POST_HIT_RECORDING",
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fifo.we.eq(self.dat_sink.stb),
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fifo.din.eq(self.dat_sink.dat),
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fifo.sink.stb.eq(data_sink.stb),
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fifo.sink.data.eq(data_sink.data),
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data_sink.ack.eq(fifo.sink.ack),
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If(~fifo.writable | (fifo.level >= self._length.storage), NextState("IDLE"))
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If(~fifo.sink.ack | (fifo.fifo.level >= self._length.storage), NextState("IDLE"))
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)
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@ -1,140 +1,73 @@
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from migen.fhdl.std import *
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from migen.fhdl.specials import Memory
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from migen.bank.description import *
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from migen.genlib.record import *
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from litescope.common import *
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class LiteScopeTerm(Module, AutoCSR):
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def __init__(self, width):
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self.width = width
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self.sink = Record(dat_layout(width))
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self.source = Record(hit_layout())
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self._trig = CSRStorage(width)
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self._mask = CSRStorage(width)
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###
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trig = self._trig.storage
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mask = self._mask.storage
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dat = self.sink.dat
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hit = self.source.hit
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self.comb += [
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hit.eq((dat & mask) == trig),
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self.source.stb.eq(self.sink.stb)
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]
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class LiteScopeRangeDetector(Module, AutoCSR):
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def __init__(self, width):
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self.width = width
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self.sink = Record(dat_layout(width))
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self.source = Record(hit_layout())
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self._low = CSRStorage(width)
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self._high = CSRStorage(width)
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###
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low = self._low.storage
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high = self._high.storage
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dat = self.sink.dat
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hit = self.source.hit
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self.comb += [
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hit.eq((dat >= low) & (dat <= high)),
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self.source.stb.eq(self.sink.stb)
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]
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class LiteScopeEdgeDetector(Module, AutoCSR):
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def __init__(self, width):
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self.width = width
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self.sink = Record(dat_layout(width))
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self.source = Record(hit_layout())
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self._rising_mask = CSRStorage(width)
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self._falling_mask = CSRStorage(width)
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self._both_mask = CSRStorage(width)
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###
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rising_mask = self._rising_mask.storage
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falling_mask = self._falling_mask.storage
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both_mask = self._both_mask.storage
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dat = self.sink.dat
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dat_d = Signal(width)
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rising_hit = Signal()
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falling_hit = Signal()
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both_hit = Signal()
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hit = self.source.hit
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self.sync += dat_d.eq(dat)
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self.comb += [
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rising_hit.eq(rising_mask & dat & ~dat_d),
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falling_hit.eq(rising_mask & ~dat & dat_d),
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both_hit.eq((both_mask & dat) != (both_mask & dat_d)),
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hit.eq(rising_hit | falling_hit | both_hit),
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self.source.stb.eq(self.sink.stb)
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]
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class LiteScopeSum(Module, AutoCSR):
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def __init__(self, ports=4):
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def __init__(self, ports):
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self.sinks = sinks = [Sink(hit_layout()) for i in range(ports)]
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self.source = source = Source(hit_layout())
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self.sinks = [Record(hit_layout()) for p in range(ports)]
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self.source = Record(hit_layout())
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self._prog_we = CSRStorage()
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self._prog_adr = CSRStorage(ports) #FIXME
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self._prog_dat = CSRStorage()
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self.prog_we = Signal()
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self.prog_adr = Signal(ports)
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self.prog_dat = Signal()
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mem = Memory(1, 2**ports)
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lut_port = mem.get_port()
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prog_port = mem.get_port(write_capable=True)
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self.specials += mem, lut_port, prog_port
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lut = mem.get_port()
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prog = mem.get_port(write_capable=True)
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self.specials += mem, lut, prog
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###
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# Lut prog
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# program port
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self.comb += [
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prog_port.we.eq(self._prog_we.storage),
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prog_port.adr.eq(self._prog_adr.storage),
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prog_port.dat_w.eq(self._prog_dat.storage)
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prog.we.eq(self.prog_we),
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prog.adr.eq(self.prog_adr),
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prog.dat_w.eq(self.prog_dat)
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]
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# Lut read
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for i, sink in enumerate(self.sinks):
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self.comb += lut_port.adr[i].eq(sink.hit)
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# LUT port
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for i, sink in enumerate(sinks):
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self.comb += lut.adr[i].eq(sink.hit)
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# Drive source
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# drive source
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self.comb += [
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self.source.stb.eq(optree("&", [sink.stb for sink in self.sinks])),
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self.source.hit.eq(lut_port.dat_r),
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source.stb.eq(optree("&", [sink.stb for sink in sinks])),
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source.hit.eq(lut.dat_r)
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]
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for i, sink in enumerate(sinks):
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self.comb += sink.ack.eq(sink.stb & source.ack)
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class LiteScopeSumCSR(Module, AutoCSR):
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def __init__(self, ports):
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LiteScopeSum.__init__(self, ports)
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self._prog_we = CSR()
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self._prog_adr = CSRStorage(ports)
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self._prog_dat = CSRStorage()
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###
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self.comb += [
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self.prog_we.eq(self._prog_we.re & self._prog_we.r),
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self.prog_adr.eq(self._prog_adr.storage),
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self.prog_dat.eq(self._prog_dat.storage)
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]
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class LiteScopeTrigger(Module, AutoCSR):
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def __init__(self, width, ports):
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self.width = width
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self.ports = ports
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def __init__(self, dw):
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self.dw = dw
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self.ports = []
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self.sink = Sink(data_layout(dw))
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self.source = Source(hit_layout())
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|
||||
self.submodules.sum = LiteScopeSum(len(ports))
|
||||
for i, port in enumerate(ports):
|
||||
setattr(self.submodules, "port"+str(i), port)
|
||||
|
||||
self.sink = Record(dat_layout(width))
|
||||
self.source = self.sum.source
|
||||
def add_port(self, port):
|
||||
setattr(self.submodules, "port"+str(len(self.ports)), port)
|
||||
self.ports.append(port)
|
||||
|
||||
def do_finalize(self):
|
||||
self.submodules.sum = LiteScopeSumCSR(len(self.ports))
|
||||
###
|
||||
|
||||
for i, port in enumerate(ports):
|
||||
for i, port in enumerate(self.ports):
|
||||
# Note: port's ack is not used and supposed to be always 1
|
||||
self.comb += [
|
||||
self.sink.connect(port.sink),
|
||||
port.source.connect(self.sum.sinks[i])
|
||||
port.sink.stb.eq(self.sink.stb),
|
||||
port.sink.data.eq(self.sink.data),
|
||||
self.sink.ack.eq(1),
|
||||
Record.connect(port.source, self.sum.sinks[i])
|
||||
]
|
||||
self.comb += Record.connect(self.sum.source, self.source)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,4 @@
|
|||
from migen.fhdl.structure import *
|
||||
from migen.bank.description import *
|
||||
from litescope.common import *
|
||||
|
||||
class LiteScopeIO(Module, AutoCSR):
|
||||
def __init__(self, width):
|
||||
|
|
|
|||
|
|
@ -1,96 +1,66 @@
|
|||
from migen.fhdl.std import *
|
||||
from migen.bank.description import *
|
||||
from migen.actorlib.fifo import AsyncFIFO
|
||||
|
||||
from litescope.common import *
|
||||
from litescope.core.trigger import LiteScopeTrigger
|
||||
from litescope.core.storage import LiteScopeRecorder, LiteScopeRunLengthEncoder
|
||||
|
||||
from mibuild.tools import write_to_file
|
||||
|
||||
def _getattr_all(l, attr):
|
||||
it = iter(l)
|
||||
r = getattr(next(it), attr)
|
||||
for e in it:
|
||||
if getattr(e, attr) != r:
|
||||
raise ValueError
|
||||
return r
|
||||
|
||||
class LiteScopeLA(Module, AutoCSR):
|
||||
def __init__(self, depth, dat, with_rle=False, clk_domain="sys", pipe=False):
|
||||
def __init__(self, layout, depth, clk_domain="sys", input_buffer=False, with_rle=False):
|
||||
self.layout = layout
|
||||
self.data = Cat(*layout)
|
||||
self.dw = flen(self.data)
|
||||
self.depth = depth
|
||||
if isinstance(dat, tuple):
|
||||
dat = Cat(*dat)
|
||||
self.with_rle = with_rle
|
||||
self.clk_domain = clk_domain
|
||||
self.pipe = pipe
|
||||
self.ports = []
|
||||
self.width = flen(dat)
|
||||
self.input_buffer = input_buffer
|
||||
|
||||
self.stb = Signal(reset=1)
|
||||
self.dat = dat
|
||||
|
||||
def add_port(self, port_class):
|
||||
port = port_class(self.width)
|
||||
self.ports.append(port)
|
||||
|
||||
def do_finalize(self):
|
||||
stb = self.stb
|
||||
dat = self.dat
|
||||
if self.pipe:
|
||||
sync = getattr(self.sync, self.clk_domain)
|
||||
stb_new = Signal()
|
||||
dat_new = Signal(flen(dat))
|
||||
sync += [
|
||||
stb_new.eq(stb),
|
||||
dat_new.eq(dat)
|
||||
]
|
||||
stb = stb_new
|
||||
dat = dat_new
|
||||
|
||||
if self.clk_domain is not "sys":
|
||||
fifo = AsyncFIFO([("dat", self.width)], 32)
|
||||
self.submodules += RenameClockDomains(fifo, {"write": self.clk_domain, "read": "sys"})
|
||||
self.comb += [
|
||||
fifo.sink.stb.eq(stb),
|
||||
fifo.sink.dat.eq(dat)
|
||||
]
|
||||
sink = Record(dat_layout(self.width))
|
||||
self.comb += [
|
||||
sink.stb.eq(fifo.source.stb),
|
||||
sink.dat.eq(fifo.source.dat),
|
||||
fifo.source.ack.eq(1)
|
||||
]
|
||||
else:
|
||||
sink = Record(dat_layout(self.width))
|
||||
self.comb += [
|
||||
sink.stb.eq(stb),
|
||||
sink.dat.eq(dat)
|
||||
]
|
||||
|
||||
self.submodules.trigger = trigger = LiteScopeTrigger(self.width, self.ports)
|
||||
self.submodules.recorder = recorder = LiteScopeRecorder(self.width, self.depth)
|
||||
self.sink = Sink(data_layout(self.dw))
|
||||
self.comb += [
|
||||
sink.connect(trigger.sink),
|
||||
trigger.source.connect(recorder.trig_sink)
|
||||
self.sink.stb.eq(1),
|
||||
self.sink.data.eq(self.data)
|
||||
]
|
||||
|
||||
self.submodules.trigger = trigger = LiteScopeTrigger(self.dw)
|
||||
self.submodules.recorder = recorder = LiteScopeRecorder(self.dw, self.depth)
|
||||
|
||||
def do_finalize(self):
|
||||
# insert Buffer on sink (optional, can be used to improve timings)
|
||||
if self.input_buffer:
|
||||
self.submodules.buffer = Buffer(self.sink.description)
|
||||
self.comb += Record.connect(self.sink, self.buffer.sink)
|
||||
self.sink = self.buffer.source
|
||||
|
||||
# clock domain crossing (optional, required when capture_clk is not sys_clk)
|
||||
# XXX : sys_clk must be faster than capture_clk, add Converter on data to remove this limitation
|
||||
if self.clk_domain is not "sys":
|
||||
self.submodules.fifo = AsyncFIFO(self.sink.description, 32)
|
||||
self.submodules += RenameClockDomains(self.fifo, {"write": self.clk_domain, "read": "sys"})
|
||||
self.comb += Record.connect(self.sink, self.fifo.sink)
|
||||
self.sink = self.fifo.source
|
||||
|
||||
# connect everything
|
||||
self.comb += [
|
||||
self.trigger.sink.stb.eq(self.sink.stb),
|
||||
self.trigger.sink.data.eq(self.sink.data),
|
||||
Record.connect(self.trigger.source, self.recorder.trigger_sink)
|
||||
]
|
||||
if self.with_rle:
|
||||
self.submodules.rle = rle = LiteScopeRunLengthEncoder(self.width)
|
||||
rle = LiteScopeRunLengthEncoder(self.dw)
|
||||
self.submodules += rle
|
||||
self.comb += [
|
||||
sink.connect(rle.sink),
|
||||
rle.source.connect(recorder.dat_sink)
|
||||
Record.connect(self.sink, rle.sink),
|
||||
Record.connect(rle.source, self.recorder.data_sink)
|
||||
]
|
||||
else:
|
||||
self.comb += sink.connect(recorder.dat_sink)
|
||||
self.comb += Record.connect(self.sink, self.recorder.data_sink)
|
||||
|
||||
def export(self, layout, vns, filename):
|
||||
def export(self, vns, filename):
|
||||
def format_line(*args):
|
||||
return ",".join(args) + "\n"
|
||||
r = ""
|
||||
r += format_line("config", "width", str(self.width))
|
||||
r += format_line("config", "dw", str(self.dw))
|
||||
r += format_line("config", "depth", str(self.depth))
|
||||
r += format_line("config", "with_rle", str(int(self.with_rle)))
|
||||
for e in layout:
|
||||
for e in self.layout:
|
||||
r += format_line("layout", vns.get_name(e), str(flen(e)))
|
||||
write_to_file(filename, r)
|
||||
|
|
|
|||
|
|
@ -121,7 +121,7 @@ class LiteScopeLADriver():
|
|||
self.get_config()
|
||||
self.get_layout()
|
||||
self.build()
|
||||
self.dat = Dat(self.width)
|
||||
self.dat = Dat(self.dw)
|
||||
|
||||
def get_config(self):
|
||||
csv_reader = csv.reader(open(self.config_csv), delimiter=',', quotechar='#')
|
||||
|
|
@ -208,11 +208,9 @@ class LiteScopeLADriver():
|
|||
|
||||
def read(self):
|
||||
self.show_state("READ")
|
||||
empty = self.recorder_read_empty.read()
|
||||
while(not empty):
|
||||
self.dat.append(self.recorder_read_dat.read())
|
||||
empty = self.recorder_read_empty.read()
|
||||
self.recorder_read_en.write(1)
|
||||
while self.recorder_source_stb.read():
|
||||
self.dat.append(self.recorder_source_data.read())
|
||||
self.recorder_source_ack.write(1)
|
||||
if self.with_rle:
|
||||
if self.use_rle:
|
||||
self.dat = self.dat.decode_rle()
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ from litescope.common import *
|
|||
from litescope.bridge.uart2wb import LiteScopeUART2WB
|
||||
from litescope.frontend.io import LiteScopeIO
|
||||
from litescope.frontend.la import LiteScopeLA
|
||||
from litescope.core.trigger import LiteScopeTerm
|
||||
from litescope.core.port import LiteScopeTermCSR
|
||||
|
||||
class _CRG(Module):
|
||||
def __init__(self, clk_in):
|
||||
|
|
@ -97,12 +97,12 @@ class LiteScopeSoC(GenSoC, AutoCSR):
|
|||
cnt0,
|
||||
cnt1
|
||||
)
|
||||
self.submodules.la = LiteScopeLA(512, self.debug)
|
||||
self.la.add_port(LiteScopeTerm)
|
||||
self.submodules.la = LiteScopeLA(self.debug, 512)
|
||||
self.la.trigger.add_port(LiteScopeTermCSR(self.la.dw))
|
||||
atexit.register(self.exit, platform)
|
||||
|
||||
def exit(self, platform):
|
||||
if platform.vns is not None:
|
||||
self.la.export(self.debug, platform.vns, "./test/la.csv")
|
||||
self.la.export(platform.vns, "./test/la.csv")
|
||||
|
||||
default_subtarget = LiteScopeSoC
|
||||
|
|
|
|||
Loading…
Reference in New Issue