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Merge pull request #1172 from stffrdhrn/or1k-marocchino-linux 

Or1k marocchino linux fixes
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enjoy-digital 2022-01-21 19:28:56 +01:00 committed by GitHub
parent 443faef33b d1746e1286
commit 44bea44be3
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 15 additions and 8 deletions
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3
litex/soc/software/bios/boot.c
View File

@ -64,7 +64,8 @@ void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, unsigned
flush_cpu_dcache(); flush_cpu_dcache();
flush_l2_cache(); flush_l2_cache();
#if defined(CONFIG_CPU_TYPE_MOR1KX) && defined(CONFIG_CPU_VARIANT_LINUX) #if (defined(CONFIG_CPU_TYPE_MOR1KX) || defined(CONFIG_CPU_TYPE_MAROCCHINO)) \
&& defined(CONFIG_CPU_VARIANT_LINUX)
/* Mainline Linux expects to have exception vector base address set to the /* Mainline Linux expects to have exception vector base address set to the
* base address of Linux kernel; it also expects to be run with an offset * base address of Linux kernel; it also expects to be run with an offset
* of 0x100. */ * of 0x100. */

20
litex/tools/litex_json2dts_linux.py
View File

@ -32,14 +32,20 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
""" """
# Boot Arguments ------------------------------------------------------------------------------- # Boot Arguments -------------------------------------------------------------------------------
cpu_architectures = {
"mor1kx": "or1k",
"marocchino": "or1k",
"vexriscv smp-linux": "riscv",
}
default_initrd_start = { default_initrd_start = {
"mor1kx": 8*mB, "or1k": 8*mB,
"vexriscv smp-linux" : 16*mB, "riscv": 16*mB,
} }
default_initrd_size = 8*mB default_initrd_size = 8*mB
cpu_arch = cpu_architectures[cpu_name]
if initrd_start is None: if initrd_start is None:
initrd_start = default_initrd_start[cpu_name] initrd_start = default_initrd_start[cpu_arch]
if initrd_size is None: if initrd_size is None:
initrd_size = default_initrd_size initrd_size = default_initrd_size
@ -76,7 +82,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
# VexRiscv-SMP # VexRiscv-SMP
# ------------ # ------------
if cpu_name == "vexriscv smp-linux": if cpu_arch == "riscv":
# Cache description. # Cache description.
cache_desc = "" cache_desc = ""
if "cpu_dcache_size" in d["constants"]: if "cpu_dcache_size" in d["constants"]:
@ -165,7 +171,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
# Mor1kx # Mor1kx
# ------ # ------
elif cpu_name == "mor1kx": elif cpu_arch == "or1k":
dts += """ dts += """
cpus {{ cpus {{
#address-cells = <1>; #address-cells = <1>;
@ -264,7 +270,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
# Interrupt Controller ------------------------------------------------------------------------- # Interrupt Controller -------------------------------------------------------------------------
if cpu_name == "vexriscv smp-linux": if cpu_arch == "riscv":
dts += """ dts += """
intc0: interrupt-controller@{plic_base:x} {{ intc0: interrupt-controller@{plic_base:x} {{
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
@ -280,7 +286,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
plic_base =d["memories"]["plic"]["base"], plic_base =d["memories"]["plic"]["base"],
cpu_mapping =("\n" + " "*20).join(["&L{} 11 &L{} 9".format(cpu, cpu) for cpu in cpus])) cpu_mapping =("\n" + " "*20).join(["&L{} 11 &L{} 9".format(cpu, cpu) for cpu in cpus]))
elif cpu_name == "mor1kx": elif cpu_arch == "or1k":
dts += """ dts += """
intc0: interrupt-controller { intc0: interrupt-controller {
interrupt-controller; interrupt-controller;