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vivado: make _build_files() a method and rename
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parent
1d1189506a
commit
4522956f11
1 changed files with 29 additions and 30 deletions
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@ -46,34 +46,6 @@ def _build_xdc(named_sc, named_pc):
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r += "\n" + "\n\n".join(named_pc)
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r += "\n" + "\n\n".join(named_pc)
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return r
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return r
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def _build_files(device, sources, vincpaths, build_name, bitstream_commands, additional_commands):
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tcl = []
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for filename, language in sources:
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tcl.append("add_files " + filename.replace("\\", "/"))
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tcl.append("read_xdc %s.xdc" %build_name)
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tcl.append("synth_design -top top -part %s -include_dirs {%s}" %(device, " ".join(vincpaths)))
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tcl.append("report_utilization -hierarchical -file %s_utilization_hierarchical_synth.rpt" %(build_name))
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tcl.append("report_utilization -file %s_utilization_synth.rpt" %(build_name))
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tcl.append("place_design")
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tcl.append("report_utilization -hierarchical -file %s_utilization_hierarchical_place.rpt" %(build_name))
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tcl.append("report_utilization -file %s_utilization_place.rpt" %(build_name))
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tcl.append("report_io -file %s_io.rpt" %(build_name))
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tcl.append("report_control_sets -verbose -file %s_control_sets.rpt" %(build_name))
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tcl.append("report_clock_utilization -file %s_clock_utilization.rpt" %(build_name))
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tcl.append("route_design")
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tcl.append("report_route_status -file %s_route_status.rpt" %(build_name))
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tcl.append("report_drc -file %s_drc.rpt" %(build_name))
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tcl.append("report_timing_summary -max_paths 10 -file %s_timing.rpt" %(build_name))
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tcl.append("report_power -file %s_power.rpt" %(build_name))
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for bitstream_command in bitstream_commands:
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tcl.append(bitstream_command.format(build_name=build_name))
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tcl.append("write_bitstream -force %s.bit " %build_name)
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for additional_command in additional_commands:
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tcl.append(additional_command.format(build_name=build_name))
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tcl.append("quit")
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tools.write_to_file(build_name + ".tcl", "\n".join(tcl))
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def _run_vivado(build_name, vivado_path, source, ver=None):
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def _run_vivado(build_name, vivado_path, source, ver=None):
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if sys.platform == "win32" or sys.platform == "cygwin":
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if sys.platform == "win32" or sys.platform == "cygwin":
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build_script_contents = "REM Autogenerated by mibuild\n"
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build_script_contents = "REM Autogenerated by mibuild\n"
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@ -98,6 +70,34 @@ class XilinxVivadoToolchain:
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self.bitstream_commands = []
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self.bitstream_commands = []
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self.additional_commands = []
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self.additional_commands = []
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def _build_batch(self, platform, sources, build_name):
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tcl = []
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for filename, language in sources:
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tcl.append("add_files " + filename.replace("\\", "/"))
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tcl.append("read_xdc %s.xdc" %build_name)
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tcl.append("synth_design -top top -part %s -include_dirs {%s}" %(platform.device, " ".join(platform.verilog_include_paths)))
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tcl.append("report_utilization -hierarchical -file %s_utilization_hierarchical_synth.rpt" %(build_name))
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tcl.append("report_utilization -file %s_utilization_synth.rpt" %(build_name))
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tcl.append("place_design")
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tcl.append("report_utilization -hierarchical -file %s_utilization_hierarchical_place.rpt" %(build_name))
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tcl.append("report_utilization -file %s_utilization_place.rpt" %(build_name))
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tcl.append("report_io -file %s_io.rpt" %(build_name))
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tcl.append("report_control_sets -verbose -file %s_control_sets.rpt" %(build_name))
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tcl.append("report_clock_utilization -file %s_clock_utilization.rpt" %(build_name))
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tcl.append("route_design")
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tcl.append("report_route_status -file %s_route_status.rpt" %(build_name))
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tcl.append("report_drc -file %s_drc.rpt" %(build_name))
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tcl.append("report_timing_summary -max_paths 10 -file %s_timing.rpt" %(build_name))
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tcl.append("report_power -file %s_power.rpt" %(build_name))
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for bitstream_command in self.bitstream_commands:
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tcl.append(bitstream_command.format(build_name=build_name))
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tcl.append("write_bitstream -force %s.bit " %build_name)
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for additional_command in self.additional_commands:
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tcl.append(additional_command.format(build_name=build_name))
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tcl.append("quit")
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tools.write_to_file(build_name + ".tcl", "\n".join(tcl))
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def build(self, platform, fragment, build_dir="build", build_name="top",
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def build(self, platform, fragment, build_dir="build", build_name="top",
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vivado_path="/opt/Xilinx/Vivado", source=True, run=True):
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vivado_path="/opt/Xilinx/Vivado", source=True, run=True):
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tools.mkdir_noerror(build_dir)
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tools.mkdir_noerror(build_dir)
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@ -111,8 +111,7 @@ class XilinxVivadoToolchain:
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v_file = build_name + ".v"
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v_file = build_name + ".v"
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tools.write_to_file(v_file, v_src)
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tools.write_to_file(v_file, v_src)
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sources = platform.sources | {(v_file, "verilog")}
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sources = platform.sources | {(v_file, "verilog")}
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_build_files(platform.device, sources, platform.verilog_include_paths, build_name,
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self._build_batch(platform, sources, build_name)
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self.bitstream_commands, self.additional_commands)
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tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
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tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
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if run:
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if run:
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_run_vivado(build_name, vivado_path, source)
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_run_vivado(build_name, vivado_path, source)
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