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use verilog namespace to export mila configuration

This commit is contained in:
Florent Kermarrec 2014-08-03 17:01:58 +02:00
parent 6ffed70b59
commit 452a4a76f3
2 changed files with 4 additions and 4 deletions
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4
README
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@ -41,8 +41,8 @@ RangeDetector and EdgeDector terms not tested.
[> Examples: [> Examples:
Have a look at http://github.com/Florent-Kermarrec/misoc-de0nano Have a look at http://github.com/Florent-Kermarrec/misoc-de0nano
miio.py : Led & Switch Test controlled by Python Host. test_miio.py : Led & Switch Test controlled by Python Host.
mila.py : Logic Analyzer controlled by Python Host. test_mila.py : Logic Analyzer controlled by Python Host.
[> Contact [> Contact
E-mail: florent@enjoy-digital.fr E-mail: florent@enjoy-digital.fr

4
miscope/mila.py
View File

@ -36,7 +36,7 @@ class MiLa(Module, AutoCSR):
recorder_dat_source = self.rle.source recorder_dat_source = self.rle.source
self.comb += recorder_dat_source.connect(recorder.dat_sink) self.comb += recorder_dat_source.connect(recorder.dat_sink)
def get_csv(self, layout): def get_csv(self, layout, ns):
r = "" r = ""
def format_line(*args): def format_line(*args):
return ",".join(args) + "\n" return ",".join(args) + "\n"
@ -46,5 +46,5 @@ class MiLa(Module, AutoCSR):
r += format_line("config", "with_rle", str(int(self.with_rle))) r += format_line("config", "with_rle", str(int(self.with_rle)))
for e in layout: for e in layout:
r += format_line("layout", e.backtrace[-1][0], str(flen(e))) r += format_line("layout", ns.get_name(e), str(flen(e)))
return r return r