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integration/soc: Avoid soc_region_cls workaround and update CPUs.

This commit is contained in:
Florent Kermarrec 2023-02-21 09:43:17 +01:00
parent c1ee154340
commit 45b9636902
6 changed files with 43 additions and 30 deletions
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9
litex/soc/cores/cpu/microwatt/core.py
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@ -18,7 +18,8 @@ from litex.build.vhd2v_converter import *
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import *
from litex.gen.common import reverse_bytes
from litex.soc.integration.soc import SoCRegion
from litex.soc.cores.cpu import CPU
# Variants -----------------------------------------------------------------------------------------
@ -144,7 +145,7 @@ class Microwatt(CPU):
self.reset_address = reset_address
assert reset_address == 0x0000_0000
def add_soc_components(self, soc, soc_region_cls):
def add_soc_components(self, soc):
if "irq" in self.variant:
self.submodules.xics = XICSSlave(
platform = self.platform,
@ -152,8 +153,8 @@ class Microwatt(CPU):
core_irq_out = self.core_ext_irq,
int_level_in = self.interrupt,
)
xicsicp_region = soc_region_cls(origin=soc.mem_map.get("xicsicp"), size=4096, cached=False)
xicsics_region = soc_region_cls(origin=soc.mem_map.get("xicsics"), size=4096, cached=False)
xicsicp_region = SoCRegion(origin=soc.mem_map.get("xicsicp"), size=4096, cached=False)
xicsics_region = SocRegion(origin=soc.mem_map.get("xicsics"), size=4096, cached=False)
soc.bus.add_slave(name="xicsicp", slave=self.xics.icp_bus, region=xicsicp_region)
soc.bus.add_slave(name="xicsics", slave=self.xics.ics_bus, region=xicsics_region)

19
litex/soc/cores/cpu/naxriscv/core.py
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@ -14,8 +14,11 @@ from migen import *
from litex.gen import *
from litex import get_data_mod
from litex.soc.interconnect import axi
from litex.soc.interconnect.csr import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32, CPU_GCC_TRIPLE_RISCV64
# Variants -----------------------------------------------------------------------------------------
@ -105,15 +108,15 @@ class NaxRiscv(CPU):
@staticmethod
def args_read(args):
print(args)
NaxRiscv.jtag_tap = args.with_jtag_tap
NaxRiscv.jtag_tap = args.with_jtag_tap
NaxRiscv.jtag_instruction = args.with_jtag_instruction
NaxRiscv.update_repo = args.update_repo
NaxRiscv.update_repo = args.update_repo
NaxRiscv.no_netlist_cache = args.no_netlist_cache
NaxRiscv.with_fpu = args.with_fpu
NaxRiscv.with_fpu = args.with_fpu
if args.scala_file:
NaxRiscv.scala_files = args.scala_file
if args.scala_args:
NaxRiscv.scala_args = args.scala_args
NaxRiscv.scala_args = args.scala_args
print(args.scala_args)
if args.xlen:
xlen = int(args.xlen)
@ -289,7 +292,7 @@ class NaxRiscv(CPU):
# Add Cluster.
platform.add_source(os.path.join(vdir, self.netlist_name + ".v"), "verilog")
def add_soc_components(self, soc, soc_region_cls):
def add_soc_components(self, soc):
# Set UART/Timer0 CSRs/IRQs to the ones used by OpenSBI.
soc.csr.add("uart", n=2)
soc.csr.add("timer0", n=3)
@ -298,7 +301,7 @@ class NaxRiscv(CPU):
soc.irq.add("timer0", n=1)
# Add OpenSBI region.
soc.bus.add_region("opensbi", soc_region_cls(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True))
soc.bus.add_region("opensbi", SoCRegion(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True))
# Define ISA.
soc.add_config("CPU_ISA", NaxRiscv.get_arch())
@ -327,7 +330,7 @@ class NaxRiscv(CPU):
o_peripheral_plic_rdata = plicbus.r.data,
o_peripheral_plic_rresp = plicbus.r.resp,
)
soc.bus.add_slave("plic", self.plicbus, region=soc_region_cls(origin=soc.mem_map.get("plic"), size=0x40_0000, cached=False))
soc.bus.add_slave("plic", self.plicbus, region=SoCRegion(origin=soc.mem_map.get("plic"), size=0x40_0000, cached=False))
if NaxRiscv.jtag_tap:
self.jtag_tms = Signal()
@ -409,7 +412,7 @@ class NaxRiscv(CPU):
o_peripheral_clint_rdata = clintbus.r.data,
o_peripheral_clint_rresp = clintbus.r.resp,
)
soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
soc.bus.add_slave("clint", clintbus, region=SoCRegion(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
self.soc = soc # FIXME: Save SoC instance to retrieve the final mem layout on finalization.
def add_memory_buses(self, address_width, data_width):

13
litex/soc/cores/cpu/openc906/core.py
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@ -10,8 +10,11 @@ import re
from migen import *
from litex import get_data_mod
from litex.soc.interconnect import axi
from litex.soc.interconnect import wishbone
from litex.soc.integration.soc import SoCRegion
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
# Helpers ------------------------------------------------------------------------------------------
@ -219,15 +222,15 @@ class OpenC906(CPU):
o_tdt_dmi_pslverr = debug_apb.pslverr,
)
def add_soc_components(self, soc, soc_region_cls):
plic = soc_region_cls(origin=soc.mem_map.get("plic"), size=0x400_0000, cached=False)
clint = soc_region_cls(origin=soc.mem_map.get("clint"), size=0x400_0000, cached=False)
soc.bus.add_region(name="plic", region=plic)
def add_soc_components(self, soc):
plic = SoCRegion(origin=soc.mem_map.get("plic"), size=0x400_0000, cached=False)
clint = SoCRegion(origin=soc.mem_map.get("clint"), size=0x400_0000, cached=False)
soc.bus.add_region(name="plic", region=plic)
soc.bus.add_region(name="clint", region=clint)
if "debug" in self.variant:
soc.bus.add_slave("riscv_dm", self.debug_bus, region=
soc_region_cls(
SoCRegion(
origin = soc.mem_map.get("riscv_dm"),
size = 0x1000,
cached = False

16
litex/soc/cores/cpu/rocket/core.py
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@ -33,12 +33,16 @@ import os
from migen import *
from litex.gen import *
from litex import get_data_mod
from litex.soc.interconnect import axi
from litex.soc.interconnect import wishbone
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
class Open(Signal): pass
from litex.soc.integration.soc import SoCRegion
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
# Variants -----------------------------------------------------------------------------------------
@ -356,14 +360,14 @@ class Rocket(CPU):
"EICG_wrapper.v",
)
def add_soc_components(self, soc, soc_region_cls):
def add_soc_components(self, soc):
# Get CPU Params.
mem_dw, mmio_dw, num_cores = CPU_PARAMS[self.variant]
# Add OpenSBI/PLIC/CLINT regions.
soc.bus.add_region("opensbi", soc_region_cls(origin=self.mem_map["main_ram"] + 0x0000_0000, size=0x20_0000, cached=False, linker=True))
soc.bus.add_region("plic", soc_region_cls(origin=soc.mem_map.get("plic"), size=0x40_0000, cached=True, linker=True))
soc.bus.add_region("clint", soc_region_cls(origin=soc.mem_map.get("clint"), size= 0x1_0000, cached=True, linker=True))
soc.bus.add_region("opensbi", SoCRegion(origin=self.mem_map["main_ram"] + 0x0000_0000, size=0x20_0000, cached=False, linker=True))
soc.bus.add_region("plic", SoCRegion(origin=soc.mem_map.get("plic"), size=0x40_0000, cached=True, linker=True))
soc.bus.add_region("clint", SoCRegion(origin=soc.mem_map.get("clint"), size= 0x1_0000, cached=True, linker=True))
# Define number of CPUs
soc.add_config("CPU_COUNT", num_cores)

10
litex/soc/cores/cpu/vexriscv_smp/core.py
View File

@ -16,6 +16,8 @@ from litex import get_data_mod
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
# VexRiscv SMP -------------------------------------------------------------------------------------
@ -385,7 +387,7 @@ class VexRiscvSMP(CPU):
# Add Cluster.
platform.add_source(os.path.join(vdir, self.cluster_name + ".v"), "verilog")
def add_soc_components(self, soc, soc_region_cls):
def add_soc_components(self, soc):
# Set UART/Timer0 CSRs/IRQs to the ones used by OpenSBI.
soc.csr.add("uart", n=2)
soc.csr.add("timer0", n=3)
@ -394,7 +396,7 @@ class VexRiscvSMP(CPU):
soc.irq.add("timer0", n=1)
# Add OpenSBI region.
soc.bus.add_region("opensbi", soc_region_cls(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True))
soc.bus.add_region("opensbi", SoCRegion(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True))
# Define number of CPUs
soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)
@ -430,7 +432,7 @@ class VexRiscvSMP(CPU):
o_plicWishbone_DAT_MISO = plicbus.dat_r,
i_plicWishbone_DAT_MOSI = plicbus.dat_w
)
soc.bus.add_slave("plic", self.plicbus, region=soc_region_cls(origin=soc.mem_map.get("plic"), size=0x40_0000, cached=False))
soc.bus.add_slave("plic", self.plicbus, region=SoCRegion(origin=soc.mem_map.get("plic"), size=0x40_0000, cached=False))
# Add CLINT as Bus Slave
self.clintbus = clintbus = wishbone.Interface()
@ -443,7 +445,7 @@ class VexRiscvSMP(CPU):
o_clintWishbone_DAT_MISO = clintbus.dat_r,
i_clintWishbone_DAT_MOSI = clintbus.dat_w,
)
soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
soc.bus.add_slave("clint", clintbus, region=SoCRegion(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
def add_memory_buses(self, address_width, data_width):
VexRiscvSMP.litedram_width = data_width

6
litex/soc/integration/soc.py
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@ -22,8 +22,6 @@ from litex.gen.fhdl.hierarchy import LiteXHierarchyExplorer
from litex.compat.soc_core import *
from litex.soc.cores import cpu
from litex.soc.interconnect.csr import *
from litex.soc.interconnect.csr_eventmanager import *
from litex.soc.interconnect import csr_bus
@ -1011,6 +1009,8 @@ class SoC(LiteXModule, SoCCoreCompat):
self.add_config("CSR_ALIGNMENT", self.csr.alignment)
def add_cpu(self, name="vexriscv", variant="standard", reset_address=None, cfu=None):
from litex.soc.cores import cpu
# Check that CPU is supported.
if name not in cpu.CPUS.keys():
supported_cpus = []
@ -1129,7 +1129,7 @@ class SoC(LiteXModule, SoCCoreCompat):
self.logger.info("CPU {} {} SoC components.".format(
colorer(name, color="underline"),
colorer("adding", color="cyan")))
self.cpu.add_soc_components(soc=self, soc_region_cls=SoCRegion) # FIXME: avoid passing SoCRegion.
self.cpu.add_soc_components(soc=self)
# Add constants.
self.add_config(f"CPU_TYPE_{name}")