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soc_core: add cpu_endianness

This commit is contained in:
Florent Kermarrec 2018-08-21 19:10:22 +02:00
parent 3877d0f111
commit 45e9a42c7e
2 changed files with 3 additions and 0 deletions
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1
litex/soc/integration/cpu_interface.py
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@ -6,6 +6,7 @@ from migen import *
from litex.soc.interconnect.csr import CSRStatus from litex.soc.interconnect.csr import CSRStatus
cpu_endianness = { cpu_endianness = {
None: "big",
"lm32": "big", "lm32": "big",
"or1k": "big", "or1k": "big",
"picorv32": "little", "picorv32": "little",

2
litex/soc/integration/soc_core.py
View File

@ -7,6 +7,7 @@ from litex.soc.cores import identifier, timer, uart
from litex.soc.cores.cpu import lm32, mor1kx, picorv32, vexriscv from litex.soc.cores.cpu import lm32, mor1kx, picorv32, vexriscv
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr
from litex.soc.integration.cpu_interface import cpu_endianness
__all__ = ["mem_decoder", "SoCCore", "soc_core_args", "soc_core_argdict"] __all__ = ["mem_decoder", "SoCCore", "soc_core_args", "soc_core_argdict"]
@ -105,6 +106,7 @@ class SoCCore(Module):
self.cpu_type = cpu_type self.cpu_type = cpu_type
self.cpu_variant = cpu_variant self.cpu_variant = cpu_variant
self.cpu_endianness = cpu_endianness[cpu_type]
if integrated_rom_size: if integrated_rom_size:
cpu_reset_address = self.mem_map["rom"] cpu_reset_address = self.mem_map["rom"]
self.cpu_reset_address = cpu_reset_address self.cpu_reset_address = cpu_reset_address