soc_core: add cpu_endianness
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@ -6,6 +6,7 @@ from migen import *
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from litex.soc.interconnect.csr import CSRStatus
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cpu_endianness = {
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None: "big",
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"lm32": "big",
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"or1k": "big",
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"picorv32": "little",
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@ -7,6 +7,7 @@ from litex.soc.cores import identifier, timer, uart
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from litex.soc.cores.cpu import lm32, mor1kx, picorv32, vexriscv
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr
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from litex.soc.integration.cpu_interface import cpu_endianness
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__all__ = ["mem_decoder", "SoCCore", "soc_core_args", "soc_core_argdict"]
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@ -105,6 +106,7 @@ class SoCCore(Module):
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self.cpu_type = cpu_type
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self.cpu_variant = cpu_variant
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self.cpu_endianness = cpu_endianness[cpu_type]
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if integrated_rom_size:
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cpu_reset_address = self.mem_map["rom"]
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self.cpu_reset_address = cpu_reset_address
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