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build/microsemi/libero_soc: able to generate design script (tcl) and design constraint (pdc) for libero soc / avalanche board.
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1 changed files with 128 additions and 10 deletions
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@ -12,8 +12,116 @@ from litex.build.generic_platform import *
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from litex.build import tools
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from litex.build.microsemi import common
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def _build_files(device, sources, vincpaths, build_name):
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print("TODO: _build_files")
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def _format_constraint(c):
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if isinstance(c, Pins):
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return "-pin_name {} ".format(c.identifiers[0])
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elif isinstance(c, IOStandard):
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return "-io_std {} ".format(c.name)
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elif isinstance(c, Misc):
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raise NotImplementedError
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def _format_pdc(signame, pin, others):
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fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)]
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r = "set_io "
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r += "-port_name {} ".format(signame)
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for c in ([Pins(pin)] + others):
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r += _format_constraint(c)
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r += "-fixed true "
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r += "\n"
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return r
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def _build_pdc(named_sc, named_pc, build_name):
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pdc = ""
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for sig, pins, others, resname in named_sc:
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if len(pins) > 1:
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for i, p in enumerate(pins):
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pdc += _format_pdc(sig + "[" + str(i) + "]", p, others)
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else:
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pdc += _format_pdc(sig, pins[0], others)
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tools.write_to_file(build_name + ".pdc", pdc)
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def _build_tcl(platform, sources, build_dir, build_name):
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tcl = []
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# create project
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tcl.append(" ".join([
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"new_project",
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"-location {./impl}",
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"-name {{{}}}".format(build_name),
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"-project_description {}",
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"-block_mode 0",
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"-standalone_peripheral_initialization 0",
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"-instantiate_in_smartdesign 1",
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"-ondemand_build_dh 0",
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"-use_enhanced_constraint_flow 0",
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"-hdl {VERILOG}",
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"-family {PolarFire}",
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"-die {}",
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"-package {}",
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"-speed {}",
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"-die_voltage {}",
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"-part_range {}",
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"-adv_options {}"
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]))
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# set device FIXME: use platform device
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tcl.append(" ".join([
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"set_device",
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"-family {PolarFire}",
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"-die {MPF300TS_ES}",
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"-package {FCG484}",
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"-speed {-1}",
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"-die_voltage {1.0}",
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"-part_range {EXT}",
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"-adv_options {IO_DEFT_STD:LVCMOS 1.8V}",
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"-adv_options {RESTRICTPROBEPINS:1}",
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"-adv_options {RESTRICTSPIPINS:0}",
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"-adv_options {TEMPR:EXT}",
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"-adv_options {UNUSED_MSS_IO_RESISTOR_PULL:None}",
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"-adv_options {VCCI_1.2_VOLTR:EXT}",
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"-adv_options {VCCI_1.5_VOLTR:EXT}",
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"-adv_options {VCCI_1.8_VOLTR:EXT}",
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"-adv_options {VCCI_2.5_VOLTR:EXT}",
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"-adv_options {VCCI_3.3_VOLTR:EXT}",
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"-adv_options {VOLTR:EXT} "
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]))
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# add files
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for filename, language, library in sources:
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filename_tcl = "{" + filename + "}"
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tcl.append("import_files -hdl_source " + filename_tcl)
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# set top
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tcl.append("set_root -module {{{}}}".format(build_name))
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# copy init files FIXME: support for include path on LiberoSoC?
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for file in os.listdir(build_dir):
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if file.endswith(".init"):
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tcl.append("file copy -- {} impl/synthesis".format(file))
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# import constraints
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tcl.append("import_files -io_pdc {{{}}}".format(build_name + ".pdc"))
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# build flow
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tcl.append("run_tool -name {CONSTRAINT_MANAGEMENT}")
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tcl.append("run_tool -name {SYNTHESIZE}")
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tcl.append(" ".join([
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"configure_tool",
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"-name {PLACEROUTE}",
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"-params {EFFORT_LEVEL:true}",
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"-params {REPAIR_MIN_DELAY:true}",
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"-params {TDPR:true}"
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]))
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tcl.append("run_tool -name {PLACEROUTE}")
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tcl.append("run_tool -name {GENERATEPROGRAMMINGDATA}")
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tcl.append("run_tool -name {GENERATEPROGRAMMINGFILE}")
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# generate tcl
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tools.write_to_file(build_name + ".tcl", "\n".join(tcl))
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def _build_script(build_name, device, toolchain_path, ver=None):
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if sys.platform in ("win32", "cygwin"):
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@ -29,6 +137,7 @@ def _build_script(build_name, device, toolchain_path, ver=None):
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force_unix=False)
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return build_script_file
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def _run_script(script):
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if sys.platform in ("win32", "cygwin"):
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shell = ["cmd", "/c"]
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@ -56,7 +165,7 @@ class MicrosemiLiberoSoCPolarfireToolchain:
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special_overrides = common.microsemi_polarfire_special_overrides
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def build(self, platform, fragment, build_dir="build", build_name="top",
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toolchain_path=None, run=True, **kwargs):
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toolchain_path=None, run=False, **kwargs):
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os.makedirs(build_dir, exist_ok=True)
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cwd = os.getcwd()
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os.chdir(build_dir)
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@ -65,20 +174,29 @@ class MicrosemiLiberoSoCPolarfireToolchain:
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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sources = platform.sources | {(v_file, "verilog", "work")}
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_build_files(platform.device, sources, platform.verilog_include_paths, build_name)
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# generate verilog
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top_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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named_sc, named_pc = platform.resolve_signals(top_output.ns)
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top_file = build_name + ".v"
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top_output.write(top_file)
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platform.add_source(top_file)
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# generate design script (tcl)
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_build_tcl(platform, platform.sources, build_dir, build_name)
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# generate design constraints (pdc)
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_build_pdc(named_sc, named_pc, build_name)
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# generate build script
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script = _build_script(build_name, platform.device, toolchain_path)
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# run
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if run:
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_run_script(script)
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os.chdir(cwd)
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return v_output.ns
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return top_output.ns
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def add_period_constraint(self, platform, clk, period):
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print("TODO: add_period_constraint")
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