boards/platforms: Add Arty S7 Board.
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# This file is Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
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_io = [
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("user_led", 0, Pins("E18"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("F13"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("E13"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("H15"), IOStandard("LVCMOS33")),
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("rgb_leds", 0,
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Subsignal("r", Pins("J15 E15")),
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Subsignal("g", Pins("G17 F18")),
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Subsignal("b", Pins("F15 E14")),
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IOStandard("LVCMOS33")
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),
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("user_sw", 0, Pins("H14"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("H18"), IOStandard("LVCMOS33")),
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("user_sw", 2, Pins("G18"), IOStandard("LVCMOS33")),
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("user_sw", 3, Pins("M5"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("G15"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("K16"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("J16"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("H13"), IOStandard("LVCMOS33")),
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("clk100", 0, Pins("R2"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("C18"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("R12")),
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Subsignal("rx", Pins("V12")),
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IOStandard("LVCMOS33")),
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("spi", 0,
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Subsignal("clk", Pins("G16")),
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Subsignal("cs_n", Pins("H16")),
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Subsignal("mosi", Pins("H17")),
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Subsignal("miso", Pins("K14")),
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IOStandard("LVCMOS33")
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),
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("spiflash_4x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("M13")),
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Subsignal("dq", Pins("K17", "K18", "L14", "M15")),
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IOStandard("LVCMOS33")
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),
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("spiflash_1x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("M13")),
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Subsignal("mosi", Pins("K17")),
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Subsignal("miso", Pins("K18")),
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Subsignal("wp", Pins("L14")),
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Subsignal("hold", Pins("M15")),
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IOStandard("LVCMOS33")
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"U2 R4 V2 V4 T3 R7 V6 T6",
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"U7 V7 P6 T5 R6 U6"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("V5 T1 U3"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("U1"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("V3"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("P7"), IOStandard("SSTL135")),
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Subsignal("cs_n", Pins("R3"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("K4 M3"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"K2 K3 L4 M6 K6 M4 L5 L6",
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"N4 R1 N1 N5 M2 P1 M1 P2"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("K1 N3"), IOStandard("DIFF_SSTL135")),
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Subsignal("dqs_n", Pins("L1 N2"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_p", Pins("R5"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("T4"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("T2"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("P5"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("J6"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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("pmoda", 0, Pins("L17 L18 M14 N14 M16 M17 M18 N18"), IOStandard("LVCMOS33")),
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("pmodb", 0, Pins("P17 P18 R18 T18 P14 P15 N15 P16"), IOStandard("LVCMOS33")),
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("pmodc", 0, Pins("U15 V16 U17 U18 U16 P13 R13 V14"), IOStandard("LVCMOS33")),
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("pmodd", 0, Pins("V15 U12 V13 T12 T13 R11 T11 U11"), IOStandard("LVCMOS33")),
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]
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 10.0
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def __init__(self, toolchain="vivado", programmer="vivado"):
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XilinxPlatform.__init__(self, "xc7s50csga324-1", _io,
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toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.programmer = programmer
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
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def create_programmer(self):
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if self.programmer == "xc3sprog":
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return XC3SProg("nexys4")
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elif self.programmer == "vivado":
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return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
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else:
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raise ValueError("{} programmer is not supported"
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.format(self.programmer))
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