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Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings 

litex_sim: add option to create SDRAM module from SPD data
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enjoy-digital 2020-04-25 08:27:00 +02:00 committed by GitHub
parent 0b3c4b50fa b0f8ee9876
commit 4608bd1864
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 11 additions and 3 deletions
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14
litex/tools/litex_sim.py
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@ -166,6 +166,7 @@ class SimSoC(SoCSDRAM):
sdram_module = "MT48LC16M16", sdram_module = "MT48LC16M16",
sdram_init = [], sdram_init = [],
sdram_data_width = 32, sdram_data_width = 32,
sdram_spd_data = None,
sdram_verbosity = 0, sdram_verbosity = 0,
**kwargs): **kwargs):
platform = Platform() platform = Platform()
@ -182,9 +183,12 @@ class SimSoC(SoCSDRAM):
# SDRAM ------------------------------------------------------------------------------------ # SDRAM ------------------------------------------------------------------------------------
if with_sdram: if with_sdram:
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
sdram_module_cls = getattr(litedram_modules, sdram_module) if sdram_spd_data is None:
sdram_rate = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype]) sdram_module_cls = getattr(litedram_modules, sdram_module)
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) sdram_rate = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype])
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
else:
sdram_module = litedram_modules.SDRAMModule.from_spd_data(sdram_spd_data, sdram_clk_freq)
phy_settings = get_sdram_phy_settings( phy_settings = get_sdram_phy_settings(
memtype = sdram_module.memtype, memtype = sdram_module.memtype,
data_width = sdram_data_width, data_width = sdram_data_width,
@ -285,6 +289,7 @@ def main():
parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip") parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width") parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
parser.add_argument("--sdram-init", default=None, help="SDRAM init file") parser.add_argument("--sdram-init", default=None, help="SDRAM init file")
parser.add_argument("--sdram-from-spd-data", default=None, help="Generate SDRAM module based on SPD data from file")
parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity") parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
@ -323,6 +328,9 @@ def main():
soc_kwargs["sdram_module"] = args.sdram_module soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width) soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity) soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
if args.sdram_from_spd_data:
with open(args.sdram_from_spd_data, "rb") as f:
soc_kwargs["sdram_spd_data"] = [int(b) for b in f.read()]
if args.with_ethernet or args.with_etherbone: if args.with_ethernet or args.with_etherbone:
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": args.remote_ip}) sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": args.remote_ip})