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soc/cpu: rename cpu.buses to cpu.periph_buses.

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This commit is contained in:
Florent Kermarrec 2020-04-27 23:08:15 +02:00
parent 05815c4ecc
commit 467fee3e23
10 changed files with 49 additions and 49 deletions
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12
litex/soc/cores/cpu/blackparrot/core.py
View file

@ -73,12 +73,12 @@ class BlackParrotRV64(CPU):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.interrupt = Signal(4)
self.idbus = idbus = wishbone.Interface(data_width=64, adr_width=37)
self.buses = [idbus]
self.platform = platform
self.variant = variant
self.reset = Signal()
self.interrupt = Signal(4)
self.idbus = idbus = wishbone.Interface(data_width=64, adr_width=37)
self.periph_buses = [idbus]
# # #

14
litex/soc/cores/cpu/lm32/core.py
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@ -34,13 +34,13 @@ class LM32(CPU):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
self.buses = [i, d]
self.platform = platform
self.variant = variant
self.reset = Signal()
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
self.periph_buses = [i, d]
# # #

12
litex/soc/cores/cpu/microwatt/core.py
View file

@ -41,12 +41,12 @@ class Microwatt(CPU):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.wb_insn = wb_insn = wishbone.Interface(data_width=64, adr_width=28)
self.wb_data = wb_data = wishbone.Interface(data_width=64, adr_width=28)
self.buses = [wb_insn, wb_data]
self.platform = platform
self.variant = variant
self.reset = Signal()
self.wb_insn = wb_insn = wishbone.Interface(data_width=64, adr_width=28)
self.wb_data = wb_data = wishbone.Interface(data_width=64, adr_width=28)
self.periph_buses = [wb_insn, wb_data]
# # #

14
litex/soc/cores/cpu/minerva/core.py
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@ -31,13 +31,13 @@ class Minerva(CPU):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.ibus = wishbone.Interface()
self.dbus = wishbone.Interface()
self.buses = [self.ibus, self.dbus]
self.interrupt = Signal(32)
self.platform = platform
self.variant = variant
self.reset = Signal()
self.ibus = wishbone.Interface()
self.dbus = wishbone.Interface()
self.periph_buses = [self.ibus, self.dbus]
self.interrupt = Signal(32)
# TODO: create variants
self.with_icache = False

14
litex/soc/cores/cpu/mor1kx/core.py
View file

@ -63,13 +63,13 @@ class MOR1KX(CPU):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.buses = [i, d]
self.interrupt = Signal(32)
self.platform = platform
self.variant = variant
self.reset = Signal()
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.periph_buses = [i, d]
self.interrupt = Signal(32)
if variant == "linux":
self.mem_map = self.mem_map_linux

14
litex/soc/cores/cpu/picorv32/core.py
View file

@ -56,13 +56,13 @@ class PicoRV32(CPU):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.idbus = idbus = wishbone.Interface()
self.buses = [idbus]
self.interrupt = Signal(32)
self.trap = Signal()
self.platform = platform
self.variant = variant
self.reset = Signal()
self.idbus = idbus = wishbone.Interface()
self.periph_buses = [idbus]
self.interrupt = Signal(32)
self.trap = Signal()
# # #

2
litex/soc/cores/cpu/rocket/core.py
View file

@ -106,7 +106,7 @@ class RocketRV64(CPU):
self.mmio_wb = mmio_wb = wishbone.Interface(data_width=mmio_dw, adr_width=32-log2_int(mmio_dw//8))
self.buses = [mmio_wb]
self.periph_buses = [mmio_wb]
# # #

12
litex/soc/cores/cpu/serv/core.py
View file

@ -31,12 +31,12 @@ class SERV(CPU):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
self.buses = [ibus, dbus]
self.platform = platform
self.variant = variant
self.reset = Signal()
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
self.periph_buses = [ibus, dbus]
# # #

2
litex/soc/cores/cpu/vexriscv/core.py
View file

@ -105,7 +105,7 @@ class VexRiscv(CPU, AutoCSR):
self.reset = Signal()
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
self.buses = [ibus, dbus]
self.periph_buses = [ibus, dbus]
self.interrupt = Signal(32)
self.cpu_params = dict(

2
litex/soc/integration/soc.py
View file

@ -781,7 +781,7 @@ class SoC(Module):
if reset_address is None:
reset_address = self.mem_map["rom"]
self.cpu.set_reset_address(reset_address)
for n, cpu_bus in enumerate(self.cpu.buses):
for n, cpu_bus in enumerate(self.cpu.periph_buses):
self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus)
self.csr.add("cpu", use_loc_if_exists=True)
if hasattr(self.cpu, "interrupt"):