soc/cpu: rename cpu.buses to cpu.periph_buses.

litex/soc/cores/cpu/blackparrot/core.py

@@ -78,7 +78,7 @@ class BlackParrotRV64(CPU):
         self.reset        = Signal()
         self.interrupt    = Signal(4)
         self.idbus        = idbus = wishbone.Interface(data_width=64, adr_width=37)
-        self.buses     = [idbus]
+        self.periph_buses = [idbus]
 
         # # #
 

litex/soc/cores/cpu/lm32/core.py

@@ -40,7 +40,7 @@ class LM32(CPU):
         self.ibus         = i = wishbone.Interface()
         self.dbus         = d = wishbone.Interface()
         self.interrupt    = Signal(32)
-        self.buses     = [i, d]
+        self.periph_buses = [i, d]
 
         # # #
 

litex/soc/cores/cpu/microwatt/core.py

@@ -46,7 +46,7 @@ class Microwatt(CPU):
         self.reset        = Signal()
         self.wb_insn      = wb_insn = wishbone.Interface(data_width=64, adr_width=28)
         self.wb_data      = wb_data = wishbone.Interface(data_width=64, adr_width=28)
-        self.buses    = [wb_insn, wb_data]
+        self.periph_buses = [wb_insn, wb_data]
 
         # # #
 

litex/soc/cores/cpu/minerva/core.py

@@ -36,7 +36,7 @@ class Minerva(CPU):
         self.reset        = Signal()
         self.ibus         = wishbone.Interface()
         self.dbus         = wishbone.Interface()
-        self.buses     = [self.ibus, self.dbus]
+        self.periph_buses = [self.ibus, self.dbus]
         self.interrupt    = Signal(32)
 
         # TODO: create variants

litex/soc/cores/cpu/mor1kx/core.py

@@ -68,7 +68,7 @@ class MOR1KX(CPU):
         self.reset        = Signal()
         self.ibus         = i = wishbone.Interface()
         self.dbus         = d = wishbone.Interface()
-        self.buses     = [i, d]
+        self.periph_buses = [i, d]
         self.interrupt    = Signal(32)
 
         if variant == "linux":

litex/soc/cores/cpu/picorv32/core.py

@@ -60,7 +60,7 @@ class PicoRV32(CPU):
         self.variant      = variant
         self.reset        = Signal()
         self.idbus        = idbus = wishbone.Interface()
-        self.buses     = [idbus]
+        self.periph_buses = [idbus]
         self.interrupt    = Signal(32)
         self.trap         = Signal()
 

litex/soc/cores/cpu/rocket/core.py

@@ -106,7 +106,7 @@ class RocketRV64(CPU):
 
         self.mmio_wb   = mmio_wb = wishbone.Interface(data_width=mmio_dw, adr_width=32-log2_int(mmio_dw//8))
 
-        self.buses     = [mmio_wb]
+        self.periph_buses = [mmio_wb]
 
         # # #
 

litex/soc/cores/cpu/serv/core.py

@@ -36,7 +36,7 @@ class SERV(CPU):
         self.reset        = Signal()
         self.ibus         = ibus = wishbone.Interface()
         self.dbus         = dbus = wishbone.Interface()
-        self.buses     = [ibus, dbus]
+        self.periph_buses = [ibus, dbus]
 
         # # #
 

litex/soc/cores/cpu/vexriscv/core.py

@@ -105,7 +105,7 @@ class VexRiscv(CPU, AutoCSR):
         self.reset            = Signal()
         self.ibus             = ibus = wishbone.Interface()
         self.dbus             = dbus = wishbone.Interface()
-        self.buses            = [ibus, dbus]
+        self.periph_buses     = [ibus, dbus]
         self.interrupt        = Signal(32)
 
         self.cpu_params = dict(

litex/soc/integration/soc.py

@@ -781,7 +781,7 @@ class SoC(Module):
             if reset_address is None:
                 reset_address = self.mem_map["rom"]
             self.cpu.set_reset_address(reset_address)
-            for n, cpu_bus in enumerate(self.cpu.buses):
+            for n, cpu_bus in enumerate(self.cpu.periph_buses):
                 self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus)
             self.csr.add("cpu", use_loc_if_exists=True)
             if hasattr(self.cpu, "interrupt"):