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soc/cores/spi_flash: add endianness parameter

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This commit is contained in:
Florent Kermarrec 2018-10-30 10:19:21 +01:00
parent 6f3131e259
commit 468780c045
1 changed files with 11 additions and 3 deletions
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14
litex/soc/cores/spi_flash.py
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@ -1,6 +1,8 @@
from migen import * from migen import *
from migen.genlib.misc import timeline from migen.genlib.misc import timeline
from litex.gen import *
from litex.soc.interconnect import wishbone from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus
@ -26,7 +28,7 @@ def _format_cmd(cmd, spi_width):
class SpiFlashDualQuad(Module, AutoCSR): class SpiFlashDualQuad(Module, AutoCSR):
def __init__(self, pads, dummy=15, div=2): def __init__(self, pads, dummy=15, div=2, endianness="big"):
""" """
Simple SPI flash. Simple SPI flash.
Supports multi-bit pseudo-parallel reads (aka Dual or Quad I/O Fast Supports multi-bit pseudo-parallel reads (aka Dual or Quad I/O Fast
@ -56,7 +58,10 @@ class SpiFlashDualQuad(Module, AutoCSR):
self.specials.dq = dq.get_tristate(pads.dq) self.specials.dq = dq.get_tristate(pads.dq)
sr = Signal(max(cmd_width, addr_width, wbone_width)) sr = Signal(max(cmd_width, addr_width, wbone_width))
self.comb += bus.dat_r.eq(sr) if endianness == "big":
self.comb += bus.dat_r.eq(sr)
else:
self.comb += bus.dat_r.eq(reverse_bytes(sr))
self.comb += [ self.comb += [
pads.clk.eq(clk), pads.clk.eq(clk),
@ -136,7 +141,10 @@ class SpiFlashSingle(Module, AutoCSR):
addr_width = 24 addr_width = 24
sr = Signal(max(cmd_width, addr_width, wbone_width)) sr = Signal(max(cmd_width, addr_width, wbone_width))
self.comb += bus.dat_r.eq(sr) if endianness == "big":
self.comb += bus.dat_r.eq(sr)
else:
self.comb += bus.dat_r.eq(reverse_bytes(sr))
self.comb += [ self.comb += [
pads.clk.eq(clk), pads.clk.eq(clk),