Merge pull request #1887 from Dolu1990/jtag

tools/litex_sim support for remote_bitbang (openocd)

litex/soc/cores/cpu/vexriscv_smp/core.py

@@ -55,6 +55,7 @@ class VexRiscvSMP(CPU):
     with_fpu             = False
     cpu_per_fpu          = 4
     with_rvc             = False
+    jtag_tap             = False
     dtlb_size            = 4
     itlb_size            = 4
     csr_base             = 0xf000_0000
@@ -90,6 +91,7 @@ class VexRiscvSMP(CPU):
         cpu_group.add_argument("--csr-base",                     default="0xf0000000", help="CSR base address.")
         cpu_group.add_argument("--clint-base",                   default="0xf0010000", help="CLINT base address.")
         cpu_group.add_argument("--plic-base",                    default="0xf0c00000", help="PLIC base address.")
+        cpu_group.add_argument("--jtag-tap",                     action="store_true", help="Add the jtag tap instead of jtag instruction interface")
 
     @staticmethod
     def args_read(args):
@@ -130,6 +132,7 @@ class VexRiscvSMP(CPU):
         if(args.csr_base):   VexRiscvSMP.csr_base   = int(args.csr_base, 16)
         if(args.clint_base): VexRiscvSMP.clint_base = int(args.clint_base, 16)
         if(args.plic_base):  VexRiscvSMP.plic_base  = int(args.plic_base, 16)
+        if(args.jtag_tap):  VexRiscvSMP.jtag_tap = int(args.jtag_tap)
 
     # ABI.
     @staticmethod
@@ -202,7 +205,8 @@ class VexRiscvSMP(CPU):
         f"{'_Fpu' + str(VexRiscvSMP.cpu_per_fpu)  if VexRiscvSMP.with_fpu else ''}" \
         f"{'_Pd'   if VexRiscvSMP.privileged_debug else ''}" \
         f"{'_Hb' + str(VexRiscvSMP.hardware_breakpoints) if VexRiscvSMP.hardware_breakpoints > 0 else ''}" \
-        f"{'_Rvc'  if VexRiscvSMP.with_rvc else ''}"
+        f"{'_Rvc'  if VexRiscvSMP.with_rvc else ''}" \
+        f"{'_JtagT'  if VexRiscvSMP.jtag_tap else ''}"
 
     # Default Configs Generation.
     @staticmethod
@@ -300,6 +304,7 @@ class VexRiscvSMP(CPU):
         gen_args.append(f"--netlist-directory={vdir}")
         gen_args.append(f"--dtlb-size={VexRiscvSMP.dtlb_size}")
         gen_args.append(f"--itlb-size={VexRiscvSMP.itlb_size}")
+        gen_args.append(f"--jtag-tap={VexRiscvSMP.jtag_tap}")
 
         cmd = 'cd {path} && sbt "runMain vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen {args}"'.format(path=os.path.join(vdir, "ext", "VexRiscv"), args=" ".join(gen_args))
         subprocess.check_call(cmd, shell=True)
@@ -310,14 +315,22 @@ class VexRiscvSMP(CPU):
         self.variant          = variant
         self.human_name       = self.human_name + "-" + self.variant.upper()
         self.reset            = Signal()
-        self.jtag_clk         = Signal()
+
-        self.jtag_enable      = Signal()
+        if VexRiscvSMP.jtag_tap:
-        self.jtag_capture     = Signal()
+            self.jtag_clk = Signal()
-        self.jtag_shift       = Signal()
+            self.jtag_tdo = Signal()
-        self.jtag_update      = Signal()
+            self.jtag_tdi = Signal()
-        self.jtag_reset       = Signal()
+            self.jtag_tms = Signal()
-        self.jtag_tdo         = Signal()
+        else:
-        self.jtag_tdi         = Signal()
+            self.jtag_clk     = Signal()
+            self.jtag_tdo     = Signal()
+            self.jtag_tdi     = Signal()
+            self.jtag_reset   = Signal()
+            self.jtag_enable  = Signal()
+            self.jtag_capture = Signal()
+            self.jtag_shift   = Signal()
+            self.jtag_update  = Signal()
+
         self.interrupt        = Signal(32)
         self.pbus             = pbus = wishbone.Interface(data_width={
             # Always 32-bit when using direct LiteDRAM interfaces.
@@ -338,16 +351,6 @@ class VexRiscvSMP(CPU):
             # Interrupts.
             i_interrupts = self.interrupt,
 
-            # JTAG.
-            i_jtag_clk          = self.jtag_clk,
-            i_debugPort_enable  = self.jtag_enable,
-            i_debugPort_capture = self.jtag_capture,
-            i_debugPort_shift   = self.jtag_shift,
-            i_debugPort_update  = self.jtag_update,
-            i_debugPort_reset   = self.jtag_reset,
-            i_debugPort_tdi     = self.jtag_tdi,
-            o_debugPort_tdo     = self.jtag_tdo,
-
             # Peripheral Bus (Master).
             o_peripheral_CYC      = pbus.cyc,
             o_peripheral_STB      = pbus.stb,
@@ -362,6 +365,25 @@ class VexRiscvSMP(CPU):
             o_peripheral_BTE      = pbus.bte
         )
 
+        if VexRiscvSMP.jtag_tap:
+            self.cpu_params.update(
+                i_debugPort_tck     = self.jtag_clk,
+                i_debugPort_tms     = self.jtag_tms,
+                i_debugPort_tdi     = self.jtag_tdi,
+                o_debugPort_tdo     = self.jtag_tdo
+            )
+        else:
+            self.cpu_params.update(
+                i_jtag_clk          = self.jtag_clk,
+                i_debugPort_enable  = self.jtag_enable,
+                i_debugPort_capture = self.jtag_capture,
+                i_debugPort_shift   = self.jtag_shift,
+                i_debugPort_update  = self.jtag_update,
+                i_debugPort_reset   = self.jtag_reset,
+                i_debugPort_tdi     = self.jtag_tdi,
+                o_debugPort_tdo     = self.jtag_tdo
+            )
+
         # DMA.
         if VexRiscvSMP.coherent_dma:
             self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width, address_width=32, addressing="word")

litex/tools/litex_sim.py

@@ -129,6 +129,14 @@ _io = [
         Subsignal("i",  Pins(32)),
     ),
 
+    # JTAG.
+    ("jtag", 0,
+        Subsignal("tck", Pins(1)),
+        Subsignal("tms", Pins(1)),
+        Subsignal("tdi", Pins(1)),
+        Subsignal("tdo", Pins(1)),
+    ),
+
     # Video (VGA).
     ("vga", 0,
         Subsignal("hsync", Pins(1)),
@@ -172,6 +180,7 @@ class SimSoC(SoCCore):
         with_video_terminal = False,
         sim_debug             = False,
         trace_reset_on        = False,
+        with_jtag             = False,
         **kwargs):
         platform     = Platform()
         sys_clk_freq = int(1e6)
@@ -264,6 +273,14 @@ class SimSoC(SoCCore):
             pads = platform.request("i2c", 0)
             self.i2c = I2CMasterSim(pads)
 
+        # JTAG -------------------------------------------------------------------------------------
+        if with_jtag:
+            jtag_pads = platform.request("jtag")
+            self.comb += self.cpu.jtag_clk.eq(jtag_pads.tck)
+            self.comb += self.cpu.jtag_tms.eq(jtag_pads.tms)
+            self.comb += self.cpu.jtag_tdi.eq(jtag_pads.tdi)
+            self.comb += jtag_pads.tdo.eq(self.cpu.jtag_tdo)
+
         # SDCard -----------------------------------------------------------------------------------
         if with_sdcard:
             self.add_sdcard("sdcard", use_emulator=True)
@@ -399,6 +416,9 @@ def sim_args(parser):
     # I2C.
     parser.add_argument("--with-i2c",             action="store_true",     help="Enable I2C support.")
 
+    # JTAG
+    parser.add_argument("--with-jtagremote",      action="store_true", help="Enable jtagremote support")
+
     # GPIO.
     parser.add_argument("--with-gpio",            action="store_true",     help="Enable Tristate GPIO (32 pins).")
 
@@ -485,6 +505,10 @@ def main():
     if args.with_i2c:
         sim_config.add_module("spdeeprom", "i2c")
 
+    # JTAG
+    if args.with_jtagremote:
+        sim_config.add_module("jtagremote", "jtag", args={'port': 44853})
+
     # Video.
     if args.with_video_framebuffer or args.with_video_terminal:
         sim_config.add_module("video", "vga")
@@ -498,6 +522,7 @@ def main():
         with_etherbone         = args.with_etherbone,
         with_analyzer          = args.with_analyzer,
         with_i2c               = args.with_i2c,
+        with_jtag              = args.with_jtagremote,
         with_sdcard            = args.with_sdcard,
         with_spi_flash         = args.with_spi_flash,
         with_gpio              = args.with_gpio,