rename bfm to hdd and clean up
This commit is contained in:
Florent Kermarrec
parent
0959f5b979
commit
46a39b7d41
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@ -1,4 +1,4 @@
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import random
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import random, copy
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from migen.fhdl.std import *
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from migen.genlib.record import *
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@ -9,7 +9,7 @@ from lib.sata.link import SATALink
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from lib.sata.transport import SATATransport
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from lib.sata.command import SATACommand
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from lib.sata.test.bfm import *
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from lib.sata.test.hdd import *
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from lib.sata.test.common import *
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class CommandTXPacket(list):
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@ -34,6 +34,7 @@ class CommandStreamer(Module):
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self.length = 0
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def send(self, packet, blocking=True):
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packet = copy.deepcopy(packet)
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self.packets.append(packet)
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if blocking:
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while packet.done == 0:
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@ -103,12 +104,13 @@ class CommandLogger(Module):
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class TB(Module):
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def __init__(self):
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self.submodules.bfm = BFM(phy_debug=False,
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self.submodules.hdd = HDD(
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phy_debug=False,
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link_random_level=0, link_debug=False,
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transport_debug=True, transport_loopback=False,
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transport_debug=False, transport_loopback=False,
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command_debug=False,
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hdd_debug=False)
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self.submodules.link = SATALink(self.bfm.phy)
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mem_debug=True)
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self.submodules.link = SATALink(self.hdd.phy)
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self.submodules.transport = SATATransport(self.link)
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self.submodules.command = SATACommand(self.transport)
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@ -120,25 +122,23 @@ class TB(Module):
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]
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def gen_simulation(self, selfp):
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self.bfm.hdd.allocate_mem(0x00000000, 64*1024*1024)
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self.hdd.allocate_mem(0x00000000, 64*1024*1024)
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selfp.command.source.ack = 1
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for i in range(100):
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yield
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streamer_packet = CommandTXPacket(write=1, address=1024, length=32, data=[i for i in range(32)])
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yield from self.streamer.send(streamer_packet)
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write_data = [i for i in range(128)]
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write_packet = CommandTXPacket(write=1, address=1024, length=len(write_data), data=write_data)
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yield from self.streamer.send(write_packet)
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yield from self.logger.receive()
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for d in self.logger.packet:
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print("%08x" %d)
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for i in range(32):
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yield
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streamer_packet = CommandTXPacket(read=1, address=1024, length=32)
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yield from self.streamer.send(streamer_packet)
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read_packet = CommandTXPacket(read=1, address=1024, length=len(write_data))
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yield from self.streamer.send(read_packet)
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yield from self.logger.receive()
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for d in self.logger.packet:
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print("%08x" %d)
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read_data = self.logger.packet
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yield from self.logger.receive()
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for d in self.logger.packet:
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print("%08x" %d)
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# check results
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s, l, e = check(write_data, read_data)
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print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=512, vcd_name="my.vcd", keep_files=True)
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@ -267,9 +267,10 @@ def get_field_data(field, packet):
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return (packet[field.dword] >> field.offset) & (2**field.width-1)
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class FIS:
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def __init__(self, packet, description):
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def __init__(self, packet, description, direction="H2D"):
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self.packet = packet
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self.description = description
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self.direction = direction
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self.decode()
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def decode(self):
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@ -281,7 +282,10 @@ class FIS:
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self.packet[v.dword] |= (getattr(self, k) << v.offset)
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def __repr__(self):
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r = "--------\n"
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if self.direction == "H2D":
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r = ">>>>>>>>\n"
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else:
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r = "<<<<<<<<\n"
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for k in sorted(self.description.keys()):
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r += k + " : 0x%x" %getattr(self,k) + "\n"
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return r
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@ -290,6 +294,7 @@ class FIS_REG_H2D(FIS):
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def __init__(self, packet=[0]*fis_reg_h2d_cmd_len):
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FIS.__init__(self, packet, fis_reg_h2d_layout)
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self.type = fis_types["REG_H2D"]
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self.direction = "H2D"
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def __repr__(self):
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r = "FIS_REG_H2D\n"
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@ -300,6 +305,7 @@ class FIS_REG_D2H(FIS):
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def __init__(self, packet=[0]*fis_reg_d2h_cmd_len):
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FIS.__init__(self, packet, fis_reg_d2h_layout)
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self.type = fis_types["REG_D2H"]
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self.direction = "D2H"
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def __repr__(self):
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r = "FIS_REG_D2H\n"
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@ -310,6 +316,7 @@ class FIS_DMA_ACTIVATE_D2H(FIS):
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def __init__(self, packet=[0]*fis_dma_activate_d2h_cmd_len):
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FIS.__init__(self, packet, fis_dma_activate_d2h_layout)
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self.type = fis_types["DMA_ACTIVATE_D2H"]
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self.direction = "D2H"
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def __repr__(self):
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r = "FIS_DMA_ACTIVATE_D2H\n"
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@ -317,8 +324,8 @@ class FIS_DMA_ACTIVATE_D2H(FIS):
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return r
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class FIS_DATA(FIS):
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def __init__(self, packet=[0]):
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FIS.__init__(self, packet, fis_data_layout)
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def __init__(self, packet=[0], direction="H2D"):
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FIS.__init__(self, packet, fis_data_layout, direction)
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self.type = fis_types["DATA"]
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def __repr__(self):
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@ -329,12 +336,15 @@ class FIS_DATA(FIS):
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return r
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class FIS_UNKNOWN(FIS):
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def __init__(self, packet=[0]):
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FIS.__init__(self, packet, {})
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def __init__(self, packet=[0], direction="H2D"):
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FIS.__init__(self, packet, {}, direction)
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def __repr__(self):
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r = "UNKNOWN\n"
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r += "--------\n"
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if self.direction == "H2D":
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r += ">>>>>>>>\\n"
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else:
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r += "<<<<<<<<\n"
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for dword in self.packet:
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r += "%08x\n" %dword
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return r
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@ -365,9 +375,9 @@ class TransportLayer(Module):
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elif fis_type == fis_types["DMA_ACTIVATE_D2H"]:
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fis = FIS_DMA_ACTIVATE_D2H(packet)
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elif fis_type == fis_types["DATA"]:
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fis = FIS_DATA(packet)
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fis = FIS_DATA(packet, direction="H2D")
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else:
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fis = FIS_UNKNOWN(packet)
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fis = FIS_UNKNOWN(packet, direction="H2D")
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if self.debug:
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print(fis)
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if self.loopback:
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@ -412,10 +422,22 @@ class HDDMemRegion:
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self.data = [0]*(length//4)
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class HDD(Module):
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def __init__(self, command, debug=False):
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self.command = command
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command.set_hdd(self)
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def __init__(self,
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phy_debug=False,
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link_debug=False, link_random_level=0,
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transport_debug=False, transport_loopback=False,
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command_debug=False,
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mem_debug=False
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):
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###
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self.submodules.phy = PHYLayer(phy_debug)
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self.submodules.link = LinkLayer(self.phy, link_debug, link_random_level)
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self.submodules.transport = TransportLayer(self.link, transport_debug, transport_loopback)
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self.submodules.command = CommandLayer(self.transport, command_debug)
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self.command.set_hdd(self)
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self.mem_debug = mem_debug
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self.mem = None
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self.wr_address = 0
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self.wr_length = 0
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@ -430,12 +452,12 @@ class HDD(Module):
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def read_dma_cmd(self, fis):
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packet = self.read_mem(fis.lba_lsb, fis.count*4)
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packet.insert(0, 0)
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return [FIS_DATA(packet), FIS_REG_D2H()]
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return [FIS_DATA(packet, direction="H2D"), FIS_REG_D2H()]
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def identify_dma_cmd(self, fis):
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packet = [i for i in range(256)]
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packet.insert(0, 0)
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return [FIS_DATA(packet), FIS_REG_D2H()]
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return [FIS_DATA(packet, direction="H2D"), FIS_REG_D2H()]
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def data_cmd(self, fis):
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self.write_mem(self.wr_address, fis.packet[1:])
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@ -446,34 +468,22 @@ class HDD(Module):
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return None
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def allocate_mem(self, base, length):
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# XXX add support for multiple memory regions
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if self.mem_debug:
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print("[HDD] : Allocating {n} bytes at 0x{a}".format(n=length, a=base))
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self.mem = HDDMemRegion(base, length)
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def write_mem(self, adr, data):
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# XXX test if adr allocated in one memory region
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if self.mem_debug:
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print("[HDD] : Writing {n} bytes at 0x{a}".format(n=len(data)*4, a=adr))
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current_adr = (adr-self.mem.base)//4
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for i in range(len(data)):
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self.mem.data[current_adr+i] = data[i]
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def read_mem(self, adr, length=1):
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# XXX test if adr allocated in one memory region
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if self.mem_debug:
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print("[HDD] : Reading {n} bytes at 0x{a}".format(n=length, a=adr))
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current_adr = (adr-self.mem.base)//4
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data = []
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for i in range(length//4):
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data.append(self.mem.data[current_adr+i])
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return data
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class BFM(Module):
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def __init__(self,
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phy_debug=False,
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link_debug=False, link_random_level=0,
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transport_debug=False, transport_loopback=False,
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command_debug=False,
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hdd_debug=False
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):
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###
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self.submodules.phy = PHYLayer(phy_debug)
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self.submodules.link = LinkLayer(self.phy, link_debug, link_random_level)
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self.submodules.transport = TransportLayer(self.link, transport_debug, transport_loopback)
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self.submodules.command = CommandLayer(self.transport, command_debug)
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self.submodules.hdd = HDD(self.command, hdd_debug)
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@ -1,4 +1,4 @@
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import random
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import random, copy
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from migen.fhdl.std import *
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from migen.genlib.record import *
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@ -7,7 +7,7 @@ from migen.sim.generic import run_simulation
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from lib.sata.common import *
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from lib.sata.link import SATALink
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from lib.sata.test.bfm import *
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from lib.sata.test.hdd import *
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from lib.sata.test.common import *
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class LinkStreamer(Module):
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@ -19,6 +19,7 @@ class LinkStreamer(Module):
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self.packet.done = 1
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def send(self, packet, blocking=True):
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packet = copy.deepcopy(packet)
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self.packets.append(packet)
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if blocking:
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while packet.done == 0:
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@ -65,9 +66,11 @@ class LinkLogger(Module):
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class TB(Module):
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def __init__(self):
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self.submodules.bfm = BFM(phy_debug=False,
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link_random_level=50, transport_debug=False, transport_loopback=True)
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self.submodules.link = SATALink(self.bfm.phy)
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self.submodules.hdd = HDD(
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phy_debug=False,
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link_random_level=50,
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transport_debug=False, transport_loopback=True)
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self.submodules.link = SATALink(self.hdd.phy)
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self.submodules.streamer = LinkStreamer()
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streamer_ack_randomizer = AckRandomizer(link_description(32), level=50)
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@ -83,11 +86,9 @@ class TB(Module):
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]
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def gen_simulation(self, selfp):
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for i in range(24):
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yield
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for i in range(8):
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streamer_packet = LinkTXPacket([i for i in range(64)])
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yield from self.streamer.send(LinkTXPacket([i for i in range(64)]))
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yield from self.streamer.send(streamer_packet)
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yield from self.logger.receive()
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# check results
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