bus/asmibus/hub: forward data and tag_call
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@ -1,4 +1,5 @@
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from migen.fhdl.structure import *
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from migen.fhdl.structure import *
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from migen.corelogic.misc import optree
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class FinalizeError(Exception):
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class FinalizeError(Exception):
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pass
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pass
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@ -119,6 +120,12 @@ class Hub:
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self.ports = []
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self.ports = []
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self.finalized = False
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self.finalized = False
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self.call = Signal()
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# tag_call is created by finalize()
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self.dat_r = Signal(BV(self.dw))
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self.dat_w = Signal(BV(self.dw))
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self.dat_wm = Signal(BV(self.dw//8))
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def get_port(self, nslots=1):
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def get_port(self, nslots=1):
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if self.finalized:
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if self.finalized:
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raise FinalizeError
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raise FinalizeError
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@ -136,6 +143,7 @@ class Hub:
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for port in self.ports:
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for port in self.ports:
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port.finalize(tagbits, base)
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port.finalize(tagbits, base)
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base += len(port.slots)
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base += len(port.slots)
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self.tag_call = Signal(BV(tagbits))
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def get_slots(self):
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def get_slots(self):
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return sum([port.slots for port in self.ports], [])
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return sum([port.slots for port in self.ports], [])
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@ -143,4 +151,16 @@ class Hub:
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def get_fragment(self):
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def get_fragment(self):
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if not self.finalized:
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if not self.finalized:
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raise FinalizeError
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raise FinalizeError
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return sum([port.get_fragment() for port in self.ports], Fragment())
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ports = sum([port.get_fragment() for port in self.ports], Fragment())
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comb = []
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for port in self.ports:
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comb += [
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port.call.eq(self.call),
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port.tag_call.eq(self.tag_call),
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port.dat_r.eq(self.dat_r)
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]
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comb += [
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self.dat_w.eq(optree("|", [port.dat_w for port in self.ports])),
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self.dat_wm.eq(optree("|", [port.dat_wm for port in self.ports]))
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]
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return ports + Fragment(comb)
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