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actorlib/dma_asmi: drive dat_wm

This commit is contained in:
Sebastien Bourdeauducq 2013-05-01 21:52:26 +02:00
parent c8810a016f
commit 471393d0f9
1 changed files with 6 additions and 2 deletions
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8
migen/actorlib/dma_asmi.py
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@ -89,7 +89,8 @@ class SequentialWriter(Module):
port.adr.eq(self.address_data.payload.a), port.adr.eq(self.address_data.payload.a),
port.we.eq(1), port.we.eq(1),
port.stb.eq(self.address_data.stb), port.stb.eq(self.address_data.stb),
self.address_data.ack.eq(port.ack) self.address_data.ack.eq(port.ack),
port.dat_wm.eq(0)
] ]
self.sync += [ self.sync += [
port.dat_w.eq(0), port.dat_w.eq(0),
@ -112,7 +113,10 @@ class _WriteSlot(Module):
drive_data = Signal() drive_data = Signal()
data_reg = Signal(port.hub.dw) data_reg = Signal(port.hub.dw)
self.comb += If(drive_data, port.dat_w.eq(data_reg)) self.comb += [
If(drive_data, port.dat_w.eq(data_reg)),
port.dat_wm.eq(0)
]
self.sync += [ self.sync += [
If(port.stb & port.ack & (port.tag_issue == (port.base + n)), If(port.stb & port.ack & (port.tag_issue == (port.base + n)),