actorlib/dma_asmi: drive dat_wm
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@ -89,7 +89,8 @@ class SequentialWriter(Module):
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port.adr.eq(self.address_data.payload.a),
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port.we.eq(1),
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port.stb.eq(self.address_data.stb),
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self.address_data.ack.eq(port.ack)
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self.address_data.ack.eq(port.ack),
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port.dat_wm.eq(0)
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]
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self.sync += [
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port.dat_w.eq(0),
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@ -112,7 +113,10 @@ class _WriteSlot(Module):
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drive_data = Signal()
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data_reg = Signal(port.hub.dw)
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self.comb += If(drive_data, port.dat_w.eq(data_reg))
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self.comb += [
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If(drive_data, port.dat_w.eq(data_reg)),
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port.dat_wm.eq(0)
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]
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self.sync += [
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If(port.stb & port.ack & (port.tag_issue == (port.base + n)),
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