use new MiSoC fifo (no flush signal)
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@ -75,7 +75,7 @@ class Recorder(Module, AutoCSR):
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###
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fifo = SyncFIFO(width, depth)
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fifo = InsertReset(SyncFIFO(width, depth))
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self.submodules += fifo
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fsm = FSM(reset_state="IDLE")
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@ -90,7 +90,7 @@ class Recorder(Module, AutoCSR):
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fsm.act("IDLE",
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If(self._r_trigger.re & self._r_trigger.r,
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NextState("PRE_HIT_RECORDING"),
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fifo.flush.eq(1),
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fifo.reset.eq(1),
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),
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fifo.re.eq(self._r_read_en.re & self._r_read_en.r),
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self._r_done.status.eq(1)
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