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lm32: replace clogb2 by builtin $clog2
This function is fixed in ISE since version 14.1 (see AR #44586). If the builtin function is used, the design can be simulated with Icarus Verilog. Signed-off-by: Michael Walle <michael@walle.cc>
This commit is contained in:
Michael Walle
Sebastien Bourdeauducq
parent
ced98d7bee
commit
47baad4fe1
9 changed files with 24 additions and 109 deletions
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@ -780,8 +780,6 @@ reg ext_break_r;
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// Functions
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/////////////////////////////////////////////////////
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`include "lm32_functions.v"
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/////////////////////////////////////////////////////
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// Instantiations
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/////////////////////////////////////////////////////
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@ -112,14 +112,14 @@ parameter bytes_per_line = 16; // Number of bytes per c
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parameter base_address = 0; // Base address of cachable memory
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parameter limit = 0; // Limit (highest address) of cachable memory
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localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
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localparam addr_set_width = clogb2(sets)-1;
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localparam addr_offset_width = $clog2(bytes_per_line)-2;
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localparam addr_set_width = $clog2(sets);
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localparam addr_offset_lsb = 2;
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localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
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localparam addr_set_lsb = (addr_offset_msb+1);
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localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
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localparam addr_tag_lsb = (addr_set_msb+1);
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localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1;
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localparam addr_tag_msb = $clog2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS);
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localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
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/////////////////////////////////////////////////////
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@ -200,8 +200,6 @@ genvar i, j;
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// Functions
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/////////////////////////////////////////////////////
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`include "lm32_functions.v"
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/////////////////////////////////////////////////////
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// Instantiations
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/////////////////////////////////////////////////////
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@ -183,8 +183,6 @@ integer state; // State of single-step FSM
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// Functions
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/////////////////////////////////////////////////////
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`include "lm32_functions.v"
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/////////////////////////////////////////////////////
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// Combinational Logic
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/////////////////////////////////////////////////////
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@ -333,8 +333,6 @@ wire select_call_immediate; // Whether to select the call im
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// Functions
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/////////////////////////////////////////////////////
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`include "lm32_functions.v"
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/////////////////////////////////////////////////////
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// Combinational logic
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/////////////////////////////////////////////////////
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@ -1,70 +0,0 @@
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// ==================================================================
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// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// ------------------------------------------------------------------
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// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// ------------------------------------------------------------------
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//
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// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
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//
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// Permission:
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//
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// Lattice Semiconductor grants permission to use this code
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// pursuant to the terms of the Lattice Semiconductor Corporation
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// Open Source License Agreement.
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//
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// Disclaimer:
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//
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// Lattice Semiconductor provides no warranty regarding the use or
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// functionality of this code. It is the user's responsibility to
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// verify the user's design for consistency and functionality through
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// the use of formal verification methods.
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//
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// --------------------------------------------------------------------
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//
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// Lattice Semiconductor Corporation
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// 5555 NE Moore Court
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// Hillsboro, OR 97214
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// U.S.A
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//
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// TEL: 1-800-Lattice (USA and Canada)
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// 503-286-8001 (other locations)
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//
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// web: http://www.latticesemi.com/
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// email: techsupport@latticesemi.com
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//
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// --------------------------------------------------------------------
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_functions.v
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// Title : Common functions
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// Version : 6.1.17
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// : Initial Release
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// Version : 7.0SP2, 3.0
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// : No Change
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// Version : 3.5
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// : Added function to generate log-of-two that rounds-up to
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// : power-of-two
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// =============================================================================
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function integer clogb2;
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input [31:0] value;
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begin
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for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
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value = value >> 1;
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end
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endfunction
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function integer clogb2_v1;
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input [31:0] value;
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reg [31:0] i;
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reg [31:0] temp;
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begin
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temp = 0;
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i = 0;
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for (i = 0; temp < value; i = i + 1)
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temp = 1<<i;
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clogb2_v1 = i-1;
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end
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endfunction
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@ -119,14 +119,14 @@ parameter bytes_per_line = 16; // Number of bytes per c
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parameter base_address = 0; // Base address of cachable memory
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parameter limit = 0; // Limit (highest address) of cachable memory
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localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
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localparam addr_set_width = clogb2(sets)-1;
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localparam addr_offset_width = $clog2(bytes_per_line)-2;
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localparam addr_set_width = $clog2(sets);
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localparam addr_offset_lsb = 2;
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localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
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localparam addr_set_lsb = (addr_offset_msb+1);
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localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
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localparam addr_tag_lsb = (addr_set_msb+1);
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localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1;
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localparam addr_tag_msb = $clog2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS);
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localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
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/////////////////////////////////////////////////////
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@ -205,8 +205,6 @@ genvar i;
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// Functions
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/////////////////////////////////////////////////////
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`include "lm32_functions.v"
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/////////////////////////////////////////////////////
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// Instantiations
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/////////////////////////////////////////////////////
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@ -179,7 +179,7 @@ parameter base_address = 0; // Base address of cacha
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parameter limit = 0; // Limit (highest address) of cachable memory
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// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
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localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
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localparam addr_offset_width = bytes_per_line == 4 ? 1 : $clog2(bytes_per_line)-2;
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localparam addr_offset_lsb = 2;
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localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
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@ -377,8 +377,6 @@ reg alternate_eba_taken;
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// Functions
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/////////////////////////////////////////////////////
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`include "lm32_functions.v"
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/////////////////////////////////////////////////////
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// Instantiations
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/////////////////////////////////////////////////////
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@ -390,18 +388,18 @@ reg alternate_eba_taken;
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// ----- Parameters -------
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.pmi_family (`LATTICE_FAMILY),
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//.pmi_addr_depth_a (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
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//.pmi_addr_width_a ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
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//.pmi_addr_depth_a (1 << $clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
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//.pmi_addr_width_a ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
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//.pmi_data_width_a (`LM32_WORD_WIDTH),
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//.pmi_addr_depth_b (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
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//.pmi_addr_width_b ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
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//.pmi_addr_depth_b (1 << $clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
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//.pmi_addr_width_b ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
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//.pmi_data_width_b (`LM32_WORD_WIDTH),
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.pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
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.pmi_addr_width_a (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
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.pmi_addr_width_a ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
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.pmi_data_width_a (`LM32_WORD_WIDTH),
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.pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
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.pmi_addr_width_b (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
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.pmi_addr_width_b ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
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.pmi_data_width_b (`LM32_WORD_WIDTH),
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.pmi_regmode_a ("noreg"),
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@ -420,8 +418,8 @@ reg alternate_eba_taken;
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.ResetB (rst_i),
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.DataInA ({32{1'b0}}),
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.DataInB (irom_store_data_m),
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.AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
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.AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
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.AddressA (pc_a[$clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
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.AddressB (irom_address_xm[$clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
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.ClockEnA (!stall_a),
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.ClockEnB (!stall_x || !stall_m),
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.WrA (`FALSE),
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@ -139,7 +139,7 @@ parameter base_address = 0; // Base address of cacha
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parameter limit = 0; // Limit (highest address) of cachable memory
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// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
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localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
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localparam addr_offset_width = bytes_per_line == 4 ? 1 : $clog2(bytes_per_line)-2;
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localparam addr_offset_lsb = 2;
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localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
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@ -282,8 +282,6 @@ reg wb_load_complete; // Indicates when a Wish
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// Functions
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/////////////////////////////////////////////////////
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`include "lm32_functions.v"
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/////////////////////////////////////////////////////
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// Instantiations
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/////////////////////////////////////////////////////
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@ -295,18 +293,18 @@ reg wb_load_complete; // Indicates when a Wish
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// ----- Parameters -------
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.pmi_family (`LATTICE_FAMILY),
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//.pmi_addr_depth_a (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
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//.pmi_addr_width_a ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
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//.pmi_addr_depth_a (1 << $clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
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//.pmi_addr_width_a ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
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//.pmi_data_width_a (`LM32_WORD_WIDTH),
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//.pmi_addr_depth_b (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
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//.pmi_addr_width_b ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
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//.pmi_addr_depth_b (1 << $clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
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//.pmi_addr_width_b ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
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//.pmi_data_width_b (`LM32_WORD_WIDTH),
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.pmi_addr_depth_a (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
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.pmi_addr_width_a (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
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.pmi_addr_width_a ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
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.pmi_data_width_a (`LM32_WORD_WIDTH),
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.pmi_addr_depth_b (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
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.pmi_addr_width_b (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
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.pmi_addr_width_b ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
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.pmi_data_width_b (`LM32_WORD_WIDTH),
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.pmi_regmode_a ("noreg"),
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@ -325,8 +323,8 @@ reg wb_load_complete; // Indicates when a Wish
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.ResetB (rst_i),
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.DataInA ({32{1'b0}}),
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.DataInB (dram_store_data_m),
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.AddressA (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
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.AddressB (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
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.AddressA (load_store_address_x[$clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
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.AddressB (load_store_address_m[$clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
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// .ClockEnA (!stall_x & (load_x | store_x)),
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.ClockEnA (!stall_x),
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.ClockEnB (!stall_m),
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@ -242,7 +242,6 @@ wire trace_bret; // Indicates a bret instruction
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// Functions
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/////////////////////////////////////////////////////
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`include "lm32_functions.v"
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/////////////////////////////////////////////////////
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// Instantiations
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/////////////////////////////////////////////////////
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