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flow/isd: add freeze register

This commit is contained in:
Sebastien Bourdeauducq 2012-08-04 23:39:52 +02:00
parent 6de517f59c
commit 47c341ecdf
1 changed files with 18 additions and 7 deletions
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25
migen/flow/isd.py
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@ -4,14 +4,15 @@ from migen.flow.hooks import DFGHook
ISD_MAGIC = 0x6ab4 ISD_MAGIC = 0x6ab4
# TODO: add freeze
class EndpointReporter: class EndpointReporter:
def __init__(self, endpoint, nbits): def __init__(self, endpoint, nbits):
self.endpoint = endpoint self.endpoint = endpoint
self.nbits = nbits
self.reset = Signal() self.reset = Signal()
self.freeze = Signal()
self._ack_count = RegisterField("ack_count", nbits, access_bus=READ_ONLY, access_dev=WRITE_ONLY) self._ack_count = RegisterField("ack_count", self.nbits, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._nack_count = RegisterField("nack_count", nbits, access_bus=READ_ONLY, access_dev=WRITE_ONLY) self._nack_count = RegisterField("nack_count", self.nbits, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._cur_stb = Field("cur_stb", 1, access_bus=READ_ONLY, access_dev=WRITE_ONLY) self._cur_stb = Field("cur_stb", 1, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._cur_ack = Field("cur_ack", 1, access_bus=READ_ONLY, access_dev=WRITE_ONLY) self._cur_ack = Field("cur_ack", 1, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._cur_status = RegisterFields("cur_status", [self._cur_stb, self._cur_ack]) self._cur_status = RegisterFields("cur_status", [self._cur_stb, self._cur_ack])
@ -22,8 +23,8 @@ class EndpointReporter:
def get_fragment(self): def get_fragment(self):
stb = Signal() stb = Signal()
ack = Signal() ack = Signal()
ack_count = self._ack_count.field.w ack_count = Signal(BV(self.nbits))
nack_count = self._nack_count.field.w nack_count = Signal(BV(self.nbits))
comb = [ comb = [
self._cur_stb.w.eq(stb), self._cur_stb.w.eq(stb),
self._cur_ack.w.eq(ack) self._cur_ack.w.eq(ack)
@ -44,6 +45,10 @@ class EndpointReporter:
nack_count.eq(nack_count + 1) nack_count.eq(nack_count + 1)
) )
) )
),
If(~self.freeze,
self._ack_count.field.w.eq(ack_count),
self._nack_count.field.w.eq(nack_count)
) )
] ]
return Fragment(comb, sync) return Fragment(comb, sync)
@ -55,6 +60,7 @@ class DFGReporter(DFGHook):
self._r_magic = RegisterField("magic", 16, access_bus=READ_ONLY, access_dev=WRITE_ONLY) self._r_magic = RegisterField("magic", 16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._r_neps = RegisterField("neps", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY) self._r_neps = RegisterField("neps", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._r_nbits = RegisterField("nbits", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY) self._r_nbits = RegisterField("nbits", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._r_freeze = RegisterField("freeze", 1)
self._r_reset = RegisterRaw("reset", 1) self._r_reset = RegisterRaw("reset", 1)
self.order = [] self.order = []
@ -69,7 +75,8 @@ class DFGReporter(DFGHook):
print("#" + str(n) + ": " + str(u) + ":" + ep + " -> " + str(v)) print("#" + str(n) + ": " + str(u) + ":" + ep + " -> " + str(v))
def get_registers(self): def get_registers(self):
registers = [self._r_magic, self._r_neps, self._r_nbits, self._r_reset] registers = [self._r_magic, self._r_neps, self._r_nbits,
self._r_freeze, self._r_reset]
for u, ep, v in self.order: for u, ep, v in self.order:
registers += self.nodepair_to_ep[(u, v)][ep].get_registers() registers += self.nodepair_to_ep[(u, v)][ep].get_registers()
return registers return registers
@ -80,5 +87,9 @@ class DFGReporter(DFGHook):
self._r_neps.field.w.eq(len(self.order)), self._r_neps.field.w.eq(len(self.order)),
self._r_nbits.field.w.eq(self._nbits) self._r_nbits.field.w.eq(self._nbits)
] ]
comb += [h.reset.eq(self._r_reset.re) for h in self.hooks_iter()] for h in self.hooks_iter():
comb += [
h.freeze.eq(self._r_freeze.field.r),
h.reset.eq(self._r_reset.re)
]
return Fragment(comb) + super().get_fragment() return Fragment(comb) + super().get_fragment()