integration/soc_core: rework interrupt assignation/reservation
The CPUs can now reserve specific interrupts with reserved_interrupts property. User can still define interrupts in SoCCore.interrupt_map (old way) or use add_interrupt method. Interrupts specific to SoCCore internal modules are allocated automatically on the remaining free interrupt ids. Priority for the interrupts allocation: - 1) CPU reserved interrupts. - 2) User interrupts. - 3) SoCCore interrupts.
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3ee9ce0529
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litex
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@ -49,7 +49,7 @@ class MOR1KX(Module):
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@property
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def reserved_interrupts(self):
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return { "nmi": 0 }
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return {"nmi": 0}
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def __init__(self, platform, reset_pc, variant="standard"):
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assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
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@ -47,7 +47,11 @@ class PicoRV32(Module):
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@property
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def reserved_interrupts(self):
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return { "picorv32_timer": 0, "picorv32_ebreak_ecall_illegal": 1, "picorv32_bus_error": 2 }
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return {
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"timer": 0,
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"ebreak_ecall_illegal": 1,
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"bus_error": 2
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}
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def __init__(self, platform, progaddr_reset, variant="standard"):
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assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
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@ -175,10 +175,6 @@ class SoCCore(Module):
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"leds": 7, # user
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}
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interrupt_map = {}
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soc_interrupt_map = {
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"timer0": 1, # LiteX Timer
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"uart": 2, # LiteX UART (IRQ 2 for UART matches mor1k standard config).
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}
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mem_map = {
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"rom": 0x00000000, # (default shadow @0x80000000)
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"sram": 0x10000000, # (default shadow @0x90000000)
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@ -195,7 +191,6 @@ class SoCCore(Module):
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with_uart=True, uart_name="serial", uart_baudrate=115200, uart_stub=False,
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ident="", ident_version=False,
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wishbone_timeout_cycles=1e6,
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reserve_nmi_interrupt=True,
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with_timer=True,
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with_ctrl=True):
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self.config = dict()
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@ -259,6 +254,8 @@ class SoCCore(Module):
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self._wb_masters = []
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self._wb_slaves = []
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self.soc_interrupt_map = {}
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if with_ctrl:
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self.submodules.ctrl = SoCController()
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@ -281,6 +278,14 @@ class SoCCore(Module):
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self.add_wb_master(self.cpu.dbus)
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if with_ctrl:
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self.comb += self.cpu.reset.eq(self.ctrl.reset)
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# add cpu reserved interrupts
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for name, _id in self.cpu.reserved_interrupts.items():
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self.add_interrupt(name, _id)
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# add user interrupts
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for name, _id in self.interrupt_map.items():
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self.add_interrupt(name, _id)
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self.config["CPU_TYPE"] = str(cpu_type).upper()
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if self.cpu_variant:
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self.config["CPU_VARIANT"] = str(cpu_type).upper()
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@ -304,18 +309,13 @@ class SoCCore(Module):
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self.add_constant("CSR_DATA_WIDTH", csr_data_width)
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self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
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if reserve_nmi_interrupt:
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self.soc_interrupt_map["nmi"] = 0 # Reserve zero for "non-maskable interrupt"
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if with_uart:
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if uart_stub:
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self.submodules.uart = uart.UARTStub()
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else:
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self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
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self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
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#else:
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# del self.soc_interrupt_map["uart"]
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self.add_interrupt("uart")
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if ident:
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if ident_version:
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@ -326,36 +326,7 @@ class SoCCore(Module):
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if with_timer:
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self.submodules.timer0 = timer.Timer()
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#else:
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# del self.soc_interrupt_map["timer0"]
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# Invert the interrupt map.
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interrupt_rmap = {}
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for mod_name, interrupt in self.interrupt_map.items():
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assert interrupt not in interrupt_rmap, (
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"Interrupt vector conflict for IRQ %s, user defined %s conflicts with user defined %s" % (
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interrupt, mod_name, interrupt_rmap[interrupt]))
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interrupt_rmap[interrupt] = mod_name
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# Add the base SoC's interrupt map
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for mod_name, interrupt in self.soc_interrupt_map.items():
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assert interrupt not in interrupt_rmap or mod_name == interrupt_rmap[interrupt], (
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"Interrupt vector conflict for IRQ %s, user defined %s conflicts with SoC inbuilt %s" % (
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interrupt, mod_name, interrupt_rmap[interrupt]))
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self.interrupt_map[mod_name] = interrupt
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interrupt_rmap[interrupt] = mod_name
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# Make sure other functions are not using this value.
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self.soc_interrupt_map = None
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# Make the interrupt vector read only
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self.interrupt_map = ReadOnlyDict(self.interrupt_map)
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# Save the interrupt reverse map
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self.interrupt_rmap = ReadOnlyDict(interrupt_rmap)
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self.add_interrupt("timer0")
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def add_cpu(self, cpu):
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if self.finalized:
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@ -369,6 +340,32 @@ class SoCCore(Module):
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self.add_cpu(cpu_or_bridge)
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self.cpu_or_bridge = self.cpu
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def add_interrupt(self, interrupt_name, interrupt_id=None):
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# check that interrupt_name is not already used
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if interrupt_name in self.soc_interrupt_map.keys():
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print(self.soc_interrupt_map)
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raise ValueError("Interrupt conflit, {} name already used".format(interrupt_name))
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# check that interrupt_id is in range
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if interrupt_id is not None and interrupt_id > 31:
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raise ValueError("{} Interrupt ID out of range ({}, max=31)".format(
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interrupt_namename, interrupt_id))
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# interrupt_id not provided: allocate interrupt to the first available id
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if interrupt_id is None:
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for n in range(32):
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if n not in self.soc_interrupt_map.values():
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self.soc_interrupt_map.update({interrupt_name: n})
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return
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raise ValueError("No more space to allocate {} interrupt".format(name))
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# interrupt_id provided: check that interrupt_id is not already used and add interrupt
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else:
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for _name, _id in self.soc_interrupt_map.items():
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if interrupt_id == _id:
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raise ValueError("Interrupt conflict, {} already used by {} interrupt".format(
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interrupt_id, _name))
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self.soc_interrupt_map.update({interrupt_name: interrupt_id})
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def initialize_rom(self, data):
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self.rom.mem.init = data
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@ -424,8 +421,8 @@ class SoCCore(Module):
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def get_constants(self):
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r = []
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for interrupt, name in sorted(self.interrupt_rmap.items()):
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r.append((name.upper() + "_INTERRUPT", interrupt))
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for _name, _id in sorted(self.soc_interrupt_map.items()):
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r.append((_name.upper() + "_INTERRUPT", _id))
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r += self._constants
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return r
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@ -482,13 +479,13 @@ class SoCCore(Module):
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# Interrupts
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if hasattr(self, "cpu"):
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if hasattr(self.cpu, "interrupt"):
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for interrupt, mod_name in sorted(self.interrupt_rmap.items()):
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if mod_name == "nmi":
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for _name, _id in sorted(self.soc_interrupt_map.items()):
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if _name in self.cpu.reserved_interrupts.keys():
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continue
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if hasattr(self, mod_name):
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mod_impl = getattr(self, mod_name)
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assert hasattr(mod_impl, 'ev'), "Submodule %s does not have EventManager (xx.ev) module" % mod_name
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self.comb += self.cpu.interrupt[interrupt].eq(mod_impl.ev.irq)
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if hasattr(self, _name):
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module = getattr(self, _name)
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assert hasattr(module, 'ev'), "Submodule %s does not have EventManager (xx.ev) module" % _name
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self.comb += self.cpu.interrupt[_id].eq(module.ev.irq)
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def build(self, *args, **kwargs):
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return self.platform.build(self, *args, **kwargs)
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@ -124,6 +124,7 @@ class SimSoC(SoCSDRAM):
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# serial
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self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
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self.submodules.uart = uart.UART(self.uart_phy)
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self.add_interrupt("uart")
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# sdram
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if with_sdram:
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