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adapt to new CSR API

This commit is contained in:
Florent Kermarrec 2013-04-14 18:23:37 +02:00
parent 4281a18deb
commit 48c1a902e5
4 changed files with 37 additions and 38 deletions
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2
miscope/bridges/uart2csr/tools/uart2Csr.py
View File

@ -65,7 +65,7 @@ class Uart2Csr:
for i in range(len(data)): for i in range(len(data)):
write_b(self.uart, data[i]) write_b(self.uart, data[i])
if self.debug: if self.debug:
print("WR %02X @ %08X" %(elt, addr + 4*i)) print("WR %02X @ %08X" %(data[i], addr + 4*i))
else: else:
write_b(self.uart, data) write_b(self.uart, data)
if self.debug: if self.debug:

10
miscope/miio.py
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@ -1,6 +1,6 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.bus import csr from migen.bus import csr
from migen.bank import description, csrgen from migen.bank import csrgen
from migen.bank.description import * from migen.bank.description import *
class MiIo: class MiIo:
@ -16,11 +16,11 @@ class MiIo:
if "I" in self.mode: if "I" in self.mode:
self.i = Signal(self.width) self.i = Signal(self.width)
self._r_i = description.RegisterField(self.width, READ_ONLY, WRITE_ONLY) self._r_i = CSRStatus(self.width)
if "O" in self.mode: if "O" in self.mode:
self.o = Signal(self.width) self.o = Signal(self.width)
self._r_o = description.RegisterField(self.width) self._r_o = CSRStorage(self.width)
self.bank = csrgen.Bank([self._r_o, self._r_i], address=self.address) self.bank = csrgen.Bank([self._r_o, self._r_i], address=self.address)
@ -28,10 +28,10 @@ class MiIo:
comb = [] comb = []
if "I" in self.mode: if "I" in self.mode:
comb += [self._r_i.field.w.eq(self.i)] comb += [self._r_i.status.eq(self.i)]
if "O" in self.mode: if "O" in self.mode:
comb += [self.o.eq(self._r_o.field.r)] comb += [self.o.eq(self._r_o.storage)]
return Fragment(comb) + self.bank.get_fragment() return Fragment(comb) + self.bank.get_fragment()
# #

37
miscope/recorder.py
View File

@ -218,17 +218,16 @@ class Recorder:
self.rle = RLE(self.width, (2**(width-2))) self.rle = RLE(self.width, (2**(width-2)))
# csr interface # csr interface
self._r_rst = RegisterField(reset=1) self._r_rst = CSRStorage(reset=1)
self._r_rle = RegisterField(reset=0) self._r_rle = CSRStorage(reset=0)
self._r_arm = RegisterField(reset=0) self._r_arm = CSRStorage(reset=0)
self._r_done = RegisterField(reset=0, access_bus=READ_ONLY, self._r_done = CSRStatus()
access_dev=WRITE_ONLY)
self._r_size = RegisterField(self.depth_width, reset=1) self._r_size = CSRStorage(self.depth_width, reset=1)
self._r_offset = RegisterField(self.depth_width, reset=1) self._r_offset = CSRStorage(self.depth_width, reset=1)
self._r_pull_stb = RegisterField(reset=0) self._r_pull_stb = CSRStorage(reset=0)
self._r_pull_dat = RegisterField(self.width, reset=1, access_bus=READ_ONLY, access_dev=WRITE_ONLY) self._r_pull_dat = CSRStatus(self.width)
self.regs = [self._r_rst, self._r_rle, self._r_arm, self._r_done, self._r_size, self._r_offset, self.regs = [self._r_rst, self._r_rle, self._r_arm, self._r_done, self._r_size, self._r_offset,
self._r_pull_stb, self._r_pull_dat] self._r_pull_stb, self._r_pull_dat]
@ -251,22 +250,22 @@ class Recorder:
def get_fragment(self): def get_fragment(self):
_pull_stb_rising = RisingEdge(self._r_pull_stb.field.r) _pull_stb_rising = RisingEdge(self._r_pull_stb.storage)
# Bank <--> Storage / Sequencer # Bank <--> Storage / Sequencer
comb = [ comb = [
self.sequencer.rst.eq(self._r_rst.field.r), self.sequencer.rst.eq(self._r_rst.storage),
self.storage.rst.eq(self._r_rst.field.r), self.storage.rst.eq(self._r_rst.storage),
self.rle.enable.eq(self._r_rle.field.r), self.rle.enable.eq(self._r_rle.storage),
self.sequencer.arm.eq(self._r_arm.field.r), self.sequencer.arm.eq(self._r_arm.storage),
self.storage.offset.eq(self._r_offset.field.r), self.storage.offset.eq(self._r_offset.storage),
self.storage.size.eq(self._r_size.field.r), self.storage.size.eq(self._r_size.storage),
self._r_done.field.w.eq(~self.sequencer.enable), self._r_done.status.eq(~self.sequencer.enable),
self.storage.pull_stb.eq(_pull_stb_rising.o), self.storage.pull_stb.eq(_pull_stb_rising.o),
self._r_pull_dat.field.w.eq(self.storage.pull_dat) self._r_pull_dat.status.eq(self.storage.pull_dat)
] ]
# Storage <--> Sequencer <--> Trigger # Storage <--> Sequencer <--> Trigger
@ -320,4 +319,6 @@ class Recorder:
self.interface.write(self.bank.get_base() + REC_READ_BASE, 1) self.interface.write(self.bank.get_base() + REC_READ_BASE, 1)
self.interface.write(self.bank.get_base() + REC_READ_BASE, 0) self.interface.write(self.bank.get_base() + REC_READ_BASE, 0)
r.append(self.interface.read_n(self.bank.get_base() + REC_READ_DATA_BASE, self.width)) r.append(self.interface.read_n(self.bank.get_base() + REC_READ_DATA_BASE, self.width))
if i%128 == 0:
print(i)
return r return r

26
miscope/trigger.py
View File

@ -40,8 +40,8 @@ class Term:
self.reg = None self.reg = None
def get_registers_comb(self): def get_registers_comb(self):
comb = [self.t.eq(self.reg.field.r[0*self.width:1*self.width])] comb = [self.t.eq(self.reg.storage[0*self.width:1*self.width])]
comb += [self.m.eq(self.reg.field.r[1*self.width:2*self.width])] comb += [self.m.eq(self.reg.storage[1*self.width:2*self.width])]
return comb return comb
def get_fragment(self): def get_fragment(self):
@ -76,8 +76,8 @@ class RangeDetector:
self.o = Signal() self.o = Signal()
def get_registers_comb(self): def get_registers_comb(self):
comb = [self.low.eq(self.reg.field.r[0*self.width:1*self.width])] comb = [self.low.eq(self.reg.storage[0*self.width:1*self.width])]
comb += [self.low.eq(self.reg.field.r[1*self.width:2*self.width])] comb += [self.low.eq(self.reg.storage[1*self.width:2*self.width])]
return comb return comb
def get_fragment(self): def get_fragment(self):
@ -122,13 +122,13 @@ class EdgeDetector:
comb = [] comb = []
i = 0 i = 0
if "R" in self.mode: if "R" in self.mode:
comb += [self.r_mask.eq(self.reg.field.r[i*self.width:(i+1)*self.width])] comb += [self.r_mask.eq(self.reg.storage[i*self.width:(i+1)*self.width])]
i += 1 i += 1
if "F" in self.mode: if "F" in self.mode:
comb += [self.f_mask.eq(self.reg.field.r[i*self.width:(i+1)*self.width])] comb += [self.f_mask.eq(self.reg.storage[i*self.width:(i+1)*self.width])]
i += 1 i += 1
if "B" in self.mode: if "B" in self.mode:
comb += [self.b_mask.eq(self.reg.field.r[i*self.width:(i+1)*self.width])] comb += [self.b_mask.eq(self.reg.storage[i*self.width:(i+1)*self.width])]
i += 1 i += 1
return comb return comb
@ -213,9 +213,9 @@ class Sum:
def get_registers_comb(self): def get_registers_comb(self):
comb = [ comb = [
self.prog_adr.eq(self.reg.field.r[0:16]), self.prog_adr.eq(self.reg.storage[0:16]),
self.prog_dat.eq(self.reg.field.r[16]), self.prog_dat.eq(self.reg.storage[16]),
self.prog_stb.eq(self.reg.field.r[17]) self.prog_stb.eq(self.reg.storage[17])
] ]
return comb return comb
@ -262,13 +262,11 @@ class Trigger:
# generate ports csr registers fields # generate ports csr registers fields
for port in self.ports: for port in self.ports:
rf = RegisterField(port.reg_p.size, reset=0, access_bus=WRITE_ONLY, rf = CSRStorage(port.reg_p.size, reset=0, name=port.reg_p.name)
access_dev=READ_ONLY, name=port.reg_p.name)
setattr(self, port.reg_p.name, rf) setattr(self, port.reg_p.name, rf)
# generate sum csr registers fields # generate sum csr registers fields
self.sum_reg = RegisterField(self.sum.reg_p.size, reset=0, access_bus=WRITE_ONLY, self.sum_reg = CSRStorage(self.sum.reg_p.size, reset=0, name=self.sum.reg_p.name)
access_dev=READ_ONLY, name=self.sum.reg_p.name)
# generate registers # generate registers
self.regs = list_regs(self.__dict__) self.regs = list_regs(self.__dict__)