adapt to new CSR API
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4281a18deb
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@ -65,7 +65,7 @@ class Uart2Csr:
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for i in range(len(data)):
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write_b(self.uart, data[i])
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if self.debug:
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print("WR %02X @ %08X" %(elt, addr + 4*i))
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print("WR %02X @ %08X" %(data[i], addr + 4*i))
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else:
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write_b(self.uart, data)
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if self.debug:
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@ -1,6 +1,6 @@
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from migen.fhdl.structure import *
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from migen.bus import csr
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from migen.bank import description, csrgen
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from migen.bank import csrgen
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from migen.bank.description import *
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class MiIo:
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@ -16,11 +16,11 @@ class MiIo:
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if "I" in self.mode:
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self.i = Signal(self.width)
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self._r_i = description.RegisterField(self.width, READ_ONLY, WRITE_ONLY)
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self._r_i = CSRStatus(self.width)
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if "O" in self.mode:
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self.o = Signal(self.width)
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self._r_o = description.RegisterField(self.width)
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self._r_o = CSRStorage(self.width)
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self.bank = csrgen.Bank([self._r_o, self._r_i], address=self.address)
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@ -28,10 +28,10 @@ class MiIo:
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comb = []
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if "I" in self.mode:
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comb += [self._r_i.field.w.eq(self.i)]
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comb += [self._r_i.status.eq(self.i)]
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if "O" in self.mode:
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comb += [self.o.eq(self._r_o.field.r)]
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comb += [self.o.eq(self._r_o.storage)]
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return Fragment(comb) + self.bank.get_fragment()
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#
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@ -218,17 +218,16 @@ class Recorder:
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self.rle = RLE(self.width, (2**(width-2)))
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# csr interface
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self._r_rst = RegisterField(reset=1)
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self._r_rle = RegisterField(reset=0)
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self._r_arm = RegisterField(reset=0)
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self._r_done = RegisterField(reset=0, access_bus=READ_ONLY,
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access_dev=WRITE_ONLY)
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self._r_rst = CSRStorage(reset=1)
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self._r_rle = CSRStorage(reset=0)
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self._r_arm = CSRStorage(reset=0)
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self._r_done = CSRStatus()
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self._r_size = RegisterField(self.depth_width, reset=1)
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self._r_offset = RegisterField(self.depth_width, reset=1)
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self._r_size = CSRStorage(self.depth_width, reset=1)
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self._r_offset = CSRStorage(self.depth_width, reset=1)
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self._r_pull_stb = RegisterField(reset=0)
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self._r_pull_dat = RegisterField(self.width, reset=1, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._r_pull_stb = CSRStorage(reset=0)
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self._r_pull_dat = CSRStatus(self.width)
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self.regs = [self._r_rst, self._r_rle, self._r_arm, self._r_done, self._r_size, self._r_offset,
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self._r_pull_stb, self._r_pull_dat]
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@ -251,22 +250,22 @@ class Recorder:
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def get_fragment(self):
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_pull_stb_rising = RisingEdge(self._r_pull_stb.field.r)
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_pull_stb_rising = RisingEdge(self._r_pull_stb.storage)
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# Bank <--> Storage / Sequencer
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comb = [
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self.sequencer.rst.eq(self._r_rst.field.r),
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self.storage.rst.eq(self._r_rst.field.r),
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self.sequencer.rst.eq(self._r_rst.storage),
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self.storage.rst.eq(self._r_rst.storage),
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self.rle.enable.eq(self._r_rle.field.r),
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self.sequencer.arm.eq(self._r_arm.field.r),
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self.storage.offset.eq(self._r_offset.field.r),
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self.storage.size.eq(self._r_size.field.r),
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self.rle.enable.eq(self._r_rle.storage),
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self.sequencer.arm.eq(self._r_arm.storage),
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self.storage.offset.eq(self._r_offset.storage),
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self.storage.size.eq(self._r_size.storage),
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self._r_done.field.w.eq(~self.sequencer.enable),
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self._r_done.status.eq(~self.sequencer.enable),
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self.storage.pull_stb.eq(_pull_stb_rising.o),
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self._r_pull_dat.field.w.eq(self.storage.pull_dat)
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self._r_pull_dat.status.eq(self.storage.pull_dat)
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]
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# Storage <--> Sequencer <--> Trigger
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@ -320,4 +319,6 @@ class Recorder:
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self.interface.write(self.bank.get_base() + REC_READ_BASE, 1)
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self.interface.write(self.bank.get_base() + REC_READ_BASE, 0)
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r.append(self.interface.read_n(self.bank.get_base() + REC_READ_DATA_BASE, self.width))
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if i%128 == 0:
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print(i)
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return r
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@ -40,8 +40,8 @@ class Term:
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self.reg = None
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def get_registers_comb(self):
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comb = [self.t.eq(self.reg.field.r[0*self.width:1*self.width])]
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comb += [self.m.eq(self.reg.field.r[1*self.width:2*self.width])]
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comb = [self.t.eq(self.reg.storage[0*self.width:1*self.width])]
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comb += [self.m.eq(self.reg.storage[1*self.width:2*self.width])]
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return comb
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def get_fragment(self):
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@ -76,8 +76,8 @@ class RangeDetector:
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self.o = Signal()
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def get_registers_comb(self):
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comb = [self.low.eq(self.reg.field.r[0*self.width:1*self.width])]
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comb += [self.low.eq(self.reg.field.r[1*self.width:2*self.width])]
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comb = [self.low.eq(self.reg.storage[0*self.width:1*self.width])]
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comb += [self.low.eq(self.reg.storage[1*self.width:2*self.width])]
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return comb
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def get_fragment(self):
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@ -122,13 +122,13 @@ class EdgeDetector:
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comb = []
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i = 0
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if "R" in self.mode:
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comb += [self.r_mask.eq(self.reg.field.r[i*self.width:(i+1)*self.width])]
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comb += [self.r_mask.eq(self.reg.storage[i*self.width:(i+1)*self.width])]
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i += 1
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if "F" in self.mode:
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comb += [self.f_mask.eq(self.reg.field.r[i*self.width:(i+1)*self.width])]
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comb += [self.f_mask.eq(self.reg.storage[i*self.width:(i+1)*self.width])]
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i += 1
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if "B" in self.mode:
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comb += [self.b_mask.eq(self.reg.field.r[i*self.width:(i+1)*self.width])]
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comb += [self.b_mask.eq(self.reg.storage[i*self.width:(i+1)*self.width])]
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i += 1
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return comb
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@ -213,9 +213,9 @@ class Sum:
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def get_registers_comb(self):
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comb = [
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self.prog_adr.eq(self.reg.field.r[0:16]),
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self.prog_dat.eq(self.reg.field.r[16]),
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self.prog_stb.eq(self.reg.field.r[17])
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self.prog_adr.eq(self.reg.storage[0:16]),
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self.prog_dat.eq(self.reg.storage[16]),
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self.prog_stb.eq(self.reg.storage[17])
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]
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return comb
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@ -262,13 +262,11 @@ class Trigger:
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# generate ports csr registers fields
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for port in self.ports:
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rf = RegisterField(port.reg_p.size, reset=0, access_bus=WRITE_ONLY,
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access_dev=READ_ONLY, name=port.reg_p.name)
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rf = CSRStorage(port.reg_p.size, reset=0, name=port.reg_p.name)
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setattr(self, port.reg_p.name, rf)
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# generate sum csr registers fields
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self.sum_reg = RegisterField(self.sum.reg_p.size, reset=0, access_bus=WRITE_ONLY,
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access_dev=READ_ONLY, name=self.sum.reg_p.name)
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self.sum_reg = CSRStorage(self.sum.reg_p.size, reset=0, name=self.sum.reg_p.name)
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# generate registers
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self.regs = list_regs(self.__dict__)
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