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genlib/fifo: width_or_layout -> width

This commit is contained in:
Sebastien Bourdeauducq 2015-10-14 21:36:44 +08:00
parent 8817716d5f
commit 48d22a7588
1 changed files with 16 additions and 17 deletions
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33
migen/genlib/fifo.py
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@ -26,38 +26,37 @@ class _FIFOInterface:
Parameters Parameters
---------- ----------
width_or_layout : int, layout width : int
Bit width for the data. Bit width for the data.
depth : int depth : int
Depth of the FIFO. Depth of the FIFO.
Attributes Attributes
---------- ----------
din : in, width_or_layout din : in, width
Input data either flat or Record structured. Input data
writable : out writable : out
There is space in the FIFO and `we` can be asserted to load new data. There is space in the FIFO and `we` can be asserted to load new data.
we : in we : in
Write enable signal to latch `din` into the FIFO. Does nothing if Write enable signal to latch `din` into the FIFO. Does nothing if
`writable` is not asserted. `writable` is not asserted.
dout : out, width_or_layout dout : out, width
Output data, same type as `din`. Only valid if `readable` is Output data. Only valid if `readable` is asserted.
asserted.
readable : out readable : out
Output data `dout` valid, FIFO not empty. Output data `dout` valid, FIFO not empty.
re : in re : in
Acknowledge `dout`. If asserted, the next entry will be Acknowledge `dout`. If asserted, the next entry will be
available on the next cycle (if `readable` is high then). available on the next cycle (if `readable` is high then).
""" """
def __init__(self, width_or_layout, depth): def __init__(self, width, depth):
self.we = Signal() self.we = Signal()
self.writable = Signal() # not full self.writable = Signal() # not full
self.re = Signal() self.re = Signal()
self.readable = Signal() # not empty self.readable = Signal() # not empty
self.din = Signal(width_or_layout) self.din = Signal(width)
self.dout = Signal(width_or_layout) self.dout = Signal(width)
self.width = width_or_layout self.width = width
class SyncFIFO(Module, _FIFOInterface): class SyncFIFO(Module, _FIFOInterface):
@ -76,8 +75,8 @@ class SyncFIFO(Module, _FIFOInterface):
""" """
__doc__ = __doc__.format(interface=_FIFOInterface.__doc__) __doc__ = __doc__.format(interface=_FIFOInterface.__doc__)
def __init__(self, width_or_layout, depth, fwft=True): def __init__(self, width, depth, fwft=True):
_FIFOInterface.__init__(self, width_or_layout, depth) _FIFOInterface.__init__(self, width, depth)
self.level = Signal(max=depth+1) self.level = Signal(max=depth+1)
self.replace = Signal() self.replace = Signal()
@ -129,9 +128,9 @@ class SyncFIFO(Module, _FIFOInterface):
class SyncFIFOBuffered(Module, _FIFOInterface): class SyncFIFOBuffered(Module, _FIFOInterface):
def __init__(self, width_or_layout, depth): def __init__(self, width, depth):
_FIFOInterface.__init__(self, width_or_layout, depth) _FIFOInterface.__init__(self, width, depth)
self.submodules.fifo = fifo = SyncFIFO(width_or_layout, depth, False) self.submodules.fifo = fifo = SyncFIFO(width, depth, False)
self.writable = fifo.writable self.writable = fifo.writable
self.din = fifo.din self.din = fifo.din
@ -162,8 +161,8 @@ class AsyncFIFO(Module, _FIFOInterface):
""" """
__doc__ = __doc__.format(interface=_FIFOInterface.__doc__) __doc__ = __doc__.format(interface=_FIFOInterface.__doc__)
def __init__(self, width_or_layout, depth): def __init__(self, width, depth):
_FIFOInterface.__init__(self, width_or_layout, depth) _FIFOInterface.__init__(self, width, depth)
### ###