genlib/fifo: width_or_layout -> width
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@ -26,38 +26,37 @@ class _FIFOInterface:
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Parameters
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Parameters
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----------
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----------
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width_or_layout : int, layout
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width : int
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Bit width for the data.
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Bit width for the data.
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depth : int
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depth : int
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Depth of the FIFO.
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Depth of the FIFO.
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Attributes
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Attributes
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----------
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----------
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din : in, width_or_layout
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din : in, width
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Input data either flat or Record structured.
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Input data
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writable : out
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writable : out
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There is space in the FIFO and `we` can be asserted to load new data.
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There is space in the FIFO and `we` can be asserted to load new data.
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we : in
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we : in
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Write enable signal to latch `din` into the FIFO. Does nothing if
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Write enable signal to latch `din` into the FIFO. Does nothing if
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`writable` is not asserted.
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`writable` is not asserted.
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dout : out, width_or_layout
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dout : out, width
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Output data, same type as `din`. Only valid if `readable` is
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Output data. Only valid if `readable` is asserted.
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asserted.
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readable : out
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readable : out
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Output data `dout` valid, FIFO not empty.
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Output data `dout` valid, FIFO not empty.
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re : in
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re : in
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Acknowledge `dout`. If asserted, the next entry will be
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Acknowledge `dout`. If asserted, the next entry will be
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available on the next cycle (if `readable` is high then).
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available on the next cycle (if `readable` is high then).
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"""
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"""
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def __init__(self, width_or_layout, depth):
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def __init__(self, width, depth):
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self.we = Signal()
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self.we = Signal()
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self.writable = Signal() # not full
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self.writable = Signal() # not full
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self.re = Signal()
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self.re = Signal()
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self.readable = Signal() # not empty
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self.readable = Signal() # not empty
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self.din = Signal(width_or_layout)
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self.din = Signal(width)
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self.dout = Signal(width_or_layout)
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self.dout = Signal(width)
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self.width = width_or_layout
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self.width = width
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class SyncFIFO(Module, _FIFOInterface):
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class SyncFIFO(Module, _FIFOInterface):
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@ -76,8 +75,8 @@ class SyncFIFO(Module, _FIFOInterface):
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"""
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"""
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__doc__ = __doc__.format(interface=_FIFOInterface.__doc__)
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__doc__ = __doc__.format(interface=_FIFOInterface.__doc__)
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def __init__(self, width_or_layout, depth, fwft=True):
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def __init__(self, width, depth, fwft=True):
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_FIFOInterface.__init__(self, width_or_layout, depth)
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_FIFOInterface.__init__(self, width, depth)
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self.level = Signal(max=depth+1)
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self.level = Signal(max=depth+1)
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self.replace = Signal()
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self.replace = Signal()
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@ -129,9 +128,9 @@ class SyncFIFO(Module, _FIFOInterface):
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class SyncFIFOBuffered(Module, _FIFOInterface):
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class SyncFIFOBuffered(Module, _FIFOInterface):
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def __init__(self, width_or_layout, depth):
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def __init__(self, width, depth):
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_FIFOInterface.__init__(self, width_or_layout, depth)
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_FIFOInterface.__init__(self, width, depth)
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self.submodules.fifo = fifo = SyncFIFO(width_or_layout, depth, False)
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self.submodules.fifo = fifo = SyncFIFO(width, depth, False)
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self.writable = fifo.writable
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self.writable = fifo.writable
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self.din = fifo.din
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self.din = fifo.din
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@ -162,8 +161,8 @@ class AsyncFIFO(Module, _FIFOInterface):
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"""
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"""
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__doc__ = __doc__.format(interface=_FIFOInterface.__doc__)
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__doc__ = __doc__.format(interface=_FIFOInterface.__doc__)
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def __init__(self, width_or_layout, depth):
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def __init__(self, width, depth):
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_FIFOInterface.__init__(self, width_or_layout, depth)
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_FIFOInterface.__init__(self, width, depth)
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###
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###
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