soc/cores: Make sure all Modules are switched to LiteXModule.

litex/soc/cores/clock/lattice_nx.py

@@ -106,7 +106,7 @@ class NXOSCA(LiteXModule):
 
 # Lattice / NX PLL ---------------------------------------------------------------------------------
 
-class NXPLL(Module):
+class NXPLL(LiteXModule):
     nclkouts_max        = 5
     clki_div_range      = ( 1, 128+1)
     clkfb_div_range     = ( 1, 128+1)

litex/soc/cores/cpu/cv32e41p/core.py

@@ -73,7 +73,7 @@ def add_manifest_sources(platform, manifest):
 
 # OBI <> Wishbone ----------------------------------------------------------------------------------
 
-class OBI2Wishbone(Module):
+class OBI2Wishbone(LiteXModule):
     def __init__(self, obi, wb):
         addr  = Signal.like(obi.addr)
         be    = Signal.like(obi.be)
@@ -123,7 +123,7 @@ class OBI2Wishbone(Module):
             )
         )
 
-class Wishbone2OBI(Module):
+class Wishbone2OBI(LiteXModule):
     def __init__(self, wb, obi):
         self.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
@@ -147,7 +147,7 @@ class Wishbone2OBI(Module):
 
 # Wishbone <> APB ----------------------------------------------------------------------------------
 
-class Wishbone2APB(Module):
+class Wishbone2APB(LiteXModule):
     def __init__(self, wb, apb):
         self.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
@@ -171,7 +171,7 @@ class Wishbone2APB(Module):
 
 # Debug Module -------------------------------------------------------------------------------------
 
-class DebugModule(Module):
+class DebugModule(LiteXModule):
     jtag_layout = [
         ("tck",  1),
         ("tms",  1),

litex/soc/cores/cpu/gowin_emcu/core.py

@@ -13,7 +13,7 @@ from litex.soc.cores.cpu import CPU
 
 # AHB Flash ----------------------------------------------------------------------------------------
 
-class AHBFlash(Module):
+class AHBFlash(LiteXModule):
     def __init__(self, bus):
         addr = Signal(13)
         read = Signal()

litex/soc/cores/cpu/ibex/core.py

@@ -45,7 +45,7 @@ obi_layout = [
     ("rdata", 32),
 ]
 
-class OBI2Wishbone(Module):
+class OBI2Wishbone(LiteXModule):
     def __init__(self, obi, wb):
         addr  = Signal.like(obi.addr)
         be    = Signal.like(obi.be)

litex/soc/cores/cpu/microwatt/core.py

@@ -236,7 +236,7 @@ class Microwatt(CPU):
 
 # XICS Slave ---------------------------------------------------------------------------------------
 
-class XICSSlave(Module, AutoCSR):
+class XICSSlave(LiteXModule):
     def __init__(self, platform, core_irq_out=Signal(), int_level_in=Signal(16), variant="standard"):
         self.variant = variant
 

litex/soc/cores/cpu/openc906/core.py

@@ -34,7 +34,7 @@ apb_layout = [
 
 # Wishbone <> APB ----------------------------------------------------------------------------------
 
-class Wishbone2APB(Module):
+class Wishbone2APB(LiteXModule):
     def __init__(self, wb, apb):
         assert wb.data_width == 32
         self.fsm = fsm = FSM(reset_state="IDLE")

litex/soc/cores/cpu/vexriscv/core.py

@@ -82,7 +82,7 @@ GCC_FLAGS = {
 
 # VexRiscv Timer -----------------------------------------------------------------------------------
 
-class VexRiscvTimer(Module, AutoCSR):
+class VexRiscvTimer(LiteXModule):
     def __init__(self):
         self._latch    = CSR()
         self._time     = CSRStatus(64)

litex/soc/cores/emif.py

@@ -11,6 +11,7 @@ from litex.gen import *
 
 from litex.soc.interconnect import wishbone
 
+# EMIF (External Memory Interface) -----------------------------------------------------------------
 
 class EMIF(LiteXModule):
     """External Memory Interface core

litex/soc/cores/spi_opi.py

@@ -14,6 +14,7 @@ from litex.soc.interconnect.csr_eventmanager import *
 
 from litex.soc.integration.doc import AutoDoc, ModuleDoc
 
+# 7-Series SPI OPI ---------------------------------------------------------------------------------
 
 class S7SPIOPI(LiteXModule):
     def __init__(self, pads,