soc/cores/clock/efinix: calc PLL parameters for Trion when feedback != INTERNAL
This commit is contained in:
Gwenhael Goavec-Merou
parent
08a62d4b5f
commit
491a207a37
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@ -45,6 +45,7 @@ class EFINIXPLL(LiteXModule):
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block["locked"] = self.name + "_locked"
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block["rstn"] = self.name + "_rstn"
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block["version"] = version
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block["feedback"] = -1
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if len(dyn_phase_shift_pads) > 0:
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block["shift_ena"] = dyn_phase_shift_pads["shift_ena"]
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block["shift"] = dyn_phase_shift_pads["shift"]
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@ -99,7 +100,7 @@ class EFINIXPLL(LiteXModule):
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self.logger.info("Use {}".format(colorer(block["resource"], "green")))
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def create_clkout(self, cd, freq, phase=0, margin=0, name="", with_reset=True, dyn_phase=False):
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def create_clkout(self, cd, freq, phase=0, margin=0, name="", with_reset=True, dyn_phase=False, is_feedback=False):
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assert self.nclkouts < self.nclkouts_max
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clk_out_name = f"{self.name}_clkout{self.nclkouts}" if name == "" else name
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@ -116,9 +117,14 @@ class EFINIXPLL(LiteXModule):
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create_clkout_log(self.logger, clk_out_name, freq, margin, self.nclkouts)
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block = self.platform.toolchain.ifacewriter.get_block(self.name)
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if is_feedback:
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assert block["feedback"] == -1
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block["feedback"] = self.nclkouts
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self.nclkouts += 1
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block = self.platform.toolchain.ifacewriter.get_block(self.name)
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block["clk_out"].append([clk_out_name, freq, phase, margin, dyn_phase])
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def extra(self, extra):
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@ -126,13 +132,176 @@ class EFINIXPLL(LiteXModule):
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block["extra"] = extra
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def compute_config(self):
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pass
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import math
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block = self.platform.toolchain.ifacewriter.get_block(self.name)
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if block["feedback"] == -1:
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return
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clks_out = {}
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for clk_id, clk in enumerate(block["clk_out"]):
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clks_out[clk_id] = {"freq": clk[1], "phase": clk[2]}
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n_out = self.nclkouts
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clk_in_freq = block["input_freq"]
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clk_fb_id = block["feedback"]
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device = self.platform.device
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vco_range = self.get_vco_freq_range(device)
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pfd_range = self.get_pfd_freq_range(device)
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pll_range = self.get_pll_freq_range(device)
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if n_out > 1:
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O_fact = [2, 4, 8]
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else:
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O_fact = [1, 2, 4, 8]
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# Pre-Divider (N).
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# -----------------
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# F_PFD is between 10e6 and 100e6
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# so limit search to only acceptable factors
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N_min = int(math.ceil(clk_in_freq / pfd_range[1]))
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N_max = int(math.floor(clk_in_freq / pfd_range[0]))
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## limit
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### when fin is below FPLL_MAX min is < 1
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if N_min < 1:
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N_min = 1
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### when fin is above FPLL_MIN and/or near max possible freq max is > 15
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if N_max > 15:
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N_max = 15
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# Multiplier (M).
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# ---------------
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## 1. needs to know all ffbk * o * cfbk acceptable to max FVCO range
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oc_range = []
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oc_min = 256*8
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oc_max = 0
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clk_fb_freq = clks_out[clk_fb_id]["freq"]
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clk_fb_phase = clks_out[clk_fb_id]["phase"]
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c_range = self.get_c_range(device, clk_fb_phase)
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# FIXME: c_range must be limited to min/max
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for c in c_range: # 1. iterate around C factor and check fPLL
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if clk_fb_freq * c < pll_range[0] or clk_fb_freq > pll_range[1]:
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continue
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for o in O_fact:
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oc = o * c
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fvco_tmp = clk_fb_freq * oc
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if fvco_tmp >= vco_range[0] and fvco_tmp <= vco_range[1]:
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oc_range.append([o, c])
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# again get range
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if oc > oc_max:
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oc_max = oc
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if oc < oc_min:
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oc_min = oc
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## 2. compute FVCO equation with informations already obtained
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## ie try all possible Fpfd freqs and try to find M with FVCO respect
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## when params are valid try to find Cx for each clock output enabled
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params_list = []
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for n in range(N_min, N_max + 1):
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fpfd_tmp = clk_in_freq / n
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# limit range using FVCO_MAX & FVCO_MIN
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# fVCO = fPFD * M * O * Cfbk
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# so:
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# fVCO
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# M = ---------------
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# fPFD * O * Cfbf
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#
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M_min = int(math.ceil(vco_range[0] / (fpfd_tmp * oc_max)))
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M_max = int(math.floor(vco_range[1] / (fpfd_tmp * oc_min)))
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if M_min < 1:
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M_min = 1
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if M_max > 255:
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M_max = 255
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for m in range(M_min, M_max + 1):
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for oc in oc_range:
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[o, c] = oc
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fvco_tmp = fpfd_tmp * m * o * c
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if fvco_tmp >= vco_range[0] and fvco_tmp <= vco_range[1]:
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# m * o * c must be below 256
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if m * o * c > 255:
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continue
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fpll_tmp = fvco_tmp / o
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cx_list = []
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for clk_id, clk_cfg in clks_out.items():
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found = False
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c_div = self.get_c_range(device, clk_cfg["phase"])
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c_list = []
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for cx in c_div:
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if clk_id == clk_fb_id and cx != c:
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continue
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clk_out = fpll_tmp / cx
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# if a C is found: no need to search more
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if clk_out == clk_cfg["freq"]:
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cx_list.append(cx)
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found = True
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break
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# no solution found for this clk: params are uncompatibles
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if found == False:
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break
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if len(cx_list) == 2:
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params_list.append([n, m, o, c, cx_list[0], cx_list[1]])
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vco_max_freq = 0
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o_div_max = 0
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params_list2 = []
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for p in params_list:
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(n, m, o, c, c0, c1) = p
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fpfd_tmp = clk_in_freq / n
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fvco_tmp = fpfd_tmp * m * o * c
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if o > o_div_max:
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o_div_max = o
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# Interface designer always select high VCO freq
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if fvco_tmp > vco_max_freq:
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vco_max_freq = fvco_tmp
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params_list2.clear()
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fpll_tmp = fvco_tmp / o
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if fvco_tmp == vco_max_freq:
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params_list2.append({
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"fvco" : fvco_tmp,
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"fpll" : fpll_tmp,
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"fpfd" : fpfd_tmp,
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"M" : m,
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"N" : n,
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"O" : o,
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"Cfbk" : c,
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"c0" : c0,
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"c1" : c1,
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})
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# Again: Interface Designer prefers high O divider.
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# -------------------------------------------------
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final_list = []
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for p in params_list2:
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if p["O"] == o_div_max:
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final_list.append(p)
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assert len(final_list) != 0
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# Select first parameters set.
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# ----------------------------
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final_list = final_list[0]
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# Fill block with PLL configuration parameters.
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# ---------------------------------------------
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block["M"] = final_list["M"]
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block["N"] = final_list["N"]
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block["O"] = final_list["O"]
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block["VCO_FREQ"] = final_list["fvco"]
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for i in range(self.nclkouts):
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block[f"CLKOUT{i}_DIV"] = final_list[f"c{i}"]
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def set_configuration(self):
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pass
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def do_finalize(self):
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pass
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# FIXME
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if not self.platform.family == "Trion":
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return
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# compute PLL configuration and arbitrary select first result
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self.compute_config()
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# Efinix / TITANIUMPLL -----------------------------------------------------------------------------
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@ -147,3 +316,35 @@ class TRIONPLL(EFINIXPLL):
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nclkouts_max = 3
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def __init__(self, platform):
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EFINIXPLL.__init__(self, platform, version="V1_V2")
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@staticmethod
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def get_vco_freq_range(device):
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FVCO_MIN = 500e6
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FVCO_MAX = 3600e6 # Local/Core, 1600 otherwise
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#FVCO_MIN = 1600e6
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return (FVCO_MIN, FVCO_MAX)
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@staticmethod
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def get_pfd_freq_range(device):
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FPFD_MIN = 10e6
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FPFD_MAX = 100e6
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return (FPFD_MIN, FPFD_MAX)
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@staticmethod
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def get_pll_freq_range(device):
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FPLL_MIN = 62.5e6
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FPLL_MAX = 1800e6 # when all C are < 64 else 1400
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return (FPLL_MIN, FPLL_MAX)
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@staticmethod
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def get_c_range(device, phase=0):
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if phase == 0:
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return [i for i in range(1, 257)]
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return {
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45: [4],
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90: [2, 4, 6],
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135: [4],
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180: [2],
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270: [2]
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}[phase]
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