soc/core: simplify/cleanup HyperRAM core
- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).
Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
This commit is contained in:
Florent Kermarrec
parent
d1502d4195
commit
4990bf33c0
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# This file is Copyright (c) 2019 Antti Lukats <antti.lukats@gmail.com>
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# This file is Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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#
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#
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#
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from migen import *
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from migen.genlib.misc import timeline
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import *
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class HyperMemporyCommon(Module):
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def __init__(self, pads):
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self.pads = pads
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class HyperRAM(HyperMemporyCommon):
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def __init__(self, pads):
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"""
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HyperRAM simple core for LiteX
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This core should always just work on any FPGA platorm it is fully vendor neutral
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No configuration, no software setup, ready after poweron, fixed latency
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"""
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HyperMemporyCommon.__init__(self, pads)
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if hasattr(pads, "rst_n"):
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self.comb += pads.rst_n.eq(1)
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if hasattr(pads, "cs1_n"):
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self.comb += pads.cs1_n.eq(1)
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# Tristate pads
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dq = TSTriple(8)
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self.specials.dq = dq.get_tristate(pads.dq)
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rwds = TSTriple(1)
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self.specials.rwds = rwds.get_tristate(pads.rwds)
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# Wishbone
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self.bus = bus = wishbone.Interface()
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sr = Signal(48)
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dq_oe = Signal(reset=0)
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rwds_oe = Signal(reset=0)
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cs_int = Signal(reset=1)
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self.comb += [
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bus.dat_r.eq(sr),
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dq.oe.eq(dq_oe),
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dq.o.eq(sr[-8:]),
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rwds.oe.eq(rwds_oe),
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pads.cs0_n.eq(cs_int)
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]
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# we generate complementaty clk out for emulated differential output
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clk_p = Signal(1)
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clk_n = Signal(1)
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self.comb += pads.clk.eq(clk_p)
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# if negative is defined drive complementary clock out
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if hasattr(pads, "clk_n"):
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self.comb += pads.clk_n.eq(clk_n)
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# 1 sys clock delay needed to adjust input timings?
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dqi = Signal(8)
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self.sync += [
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dqi.eq(dq.i)
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]
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# hyper RAM clock generator and 48 bit byte shifter
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i = Signal(max=4)
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self.sync += [
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If(i == 0,
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sr.eq(Cat(dqi, sr[:-8])),
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),
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If(i == 1,
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clk_p.eq(~cs_int), # 1
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clk_n.eq(cs_int) # 0
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),
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If(i == 2,
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sr.eq(Cat(dqi, sr[:-8]))
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),
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If(i == 3,
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i.eq(0),
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clk_p.eq(0), # 1
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clk_n.eq(1) # 0
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).Else(
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i.eq(i + 1)
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)
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]
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# signals to use CA or data to write
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CA = Signal(48)
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# combine bits to create CA bytes
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self.comb += [
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CA[47].eq(~self.bus.we),
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CA[45].eq(1),
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CA[16:35].eq(self.bus.adr[2:21]),
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CA[1:3].eq(self.bus.adr[0:2]),
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CA[0].eq(0),
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]
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z = Replicate(0, 16)
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seq = [
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(3, []),
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(12, [cs_int.eq(0), dq_oe.eq(1), sr.eq(CA)]), # 6 clock edges for command transmit
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(44, [dq_oe.eq(0)]), # 6+6 latency default
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(2, [dq_oe.eq(self.bus.we), rwds_oe.eq(self.bus.we), rwds.o.eq(~bus.sel[0]), sr.eq(Cat(z, self.bus.dat_w))]), # 4 edges to write data
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(2, [rwds.o.eq(~bus.sel[1])]), # 4 edges to write data
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(2, [rwds.o.eq(~bus.sel[2])]), # 4 edges to write data
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(2, [rwds.o.eq(~bus.sel[3])]), # 4 edges to write data
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(2, [cs_int.eq(1), rwds_oe.eq(0), dq_oe.eq(0)]),
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(1, [bus.ack.eq(1)]), # is 1 also OK?
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(1, [bus.ack.eq(0)]), #
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(0, []),
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]
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t, tseq = 0, []
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for dt, a in seq:
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tseq.append((t, a))
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t += dt
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self.sync += timeline(bus.cyc & bus.stb & (i == 1), tseq)
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@ -0,0 +1,107 @@
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# This file is Copyright (c) 2019 Antti Lukats <antti.lukats@gmail.com>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from migen import *
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from migen.genlib.misc import timeline
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from migen.genlib.io import DifferentialOutput
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from litex.soc.interconnect import wishbone
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# HyperRAM -----------------------------------------------------------------------------------------
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class HyperRAM(Module):
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"""HyperRAM
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Provides a very simple/minimal HyperRAM core that should work with all FPGA/HyperRam chips:
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- FPGA vendor agnostic.
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- no setup/chip configuration (use default latency).
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This core favrors portability and ease of use over performance.
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"""
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def __init__(self, pads):
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self.pads = pads
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self.bus = bus = wishbone.Interface()
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# # #
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clk = Signal()
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clk_phase = Signal(2)
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cs = Signal()
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ca = Signal(48)
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sr = Signal(48)
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dq = self.add_tristate(pads.dq) if not hasattr(pads.dq, "oe") else pads.dq
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rwds = self.add_tristate(pads.rwds) if not hasattr(pads.rwds, "oe") else pads.rwds
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# Drive rst_n, cs_n, clk from internal signals ---------------------------------------------
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if hasattr(pads, "rst_n"):
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self.comb += pads.rst_n.eq(1)
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self.comb += pads.cs_n[0].eq(~cs)
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assert len(pads.cs_n) <= 2
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if len(pads.cs_n) == 2:
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self.comb += pads.cs_n[1].eq(1)
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if hasattr(pads, "clk"):
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self.comb += pads.clk.eq(clk)
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else:
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self.specials += DifferentialOutput(clk, pads.clk_p, pads.clk_n)
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# Clock Generation (sys_clk/4) -------------------------------------------------------------
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self.sync += clk_phase.eq(clk_phase + 1)
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cases = {}
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cases[1] = clk.eq(cs) # Set pads clk on 90° (if cs is set)
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cases[3] = clk.eq(0) # Clear pads clk on 270°
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self.sync += Case(clk_phase, cases)
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# Data Shift Register (for write and read) -------------------------------------------------
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dqi = Signal(8)
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self.sync += dqi.eq(dq.i) # Sample on 90° and 270°
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cases = {}
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cases[0] = sr.eq(Cat(dqi, sr[:-8])) # Shift on 0°
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cases[2] = sr.eq(Cat(dqi, sr[:-8])) # Shift on 180°
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self.sync += Case(clk_phase, cases)
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self.comb += [
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bus.dat_r.eq(sr), # To Wisbone
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dq.o.eq(sr[-8:]), # To HyperRAM
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]
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# Command generation -----------------------------------------------------------------------
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self.comb += [
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ca[47].eq(~self.bus.we), # R/W#
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ca[45].eq(1), # Burst Type (Linear)
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ca[16:35].eq(self.bus.adr[2:21]), # Row & Upper Column Address
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ca[1:3].eq(self.bus.adr[0:2]), # Lower Column Address
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ca[0].eq(0), # Lower Column Address
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]
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# Sequencer --------------------------------------------------------------------------------
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dt_seq = [
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# DT, Action
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(3, []),
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(12, [cs.eq(1), dq.oe.eq(1), sr.eq(ca)]), # Command: 6 clk
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(44, [dq.oe.eq(0)]), # Latency(default): 2*6 clk
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(2, [dq.oe.eq(self.bus.we), # Write/Read data byte: 2 clk
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sr[:16].eq(0),
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sr[16:].eq(self.bus.dat_w),
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rwds.oe.eq(self.bus.we),
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rwds.o.eq(~bus.sel[0])]),
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(2, [rwds.o.eq(~bus.sel[1])]), # Write/Read data byte: 2 clk
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(2, [rwds.o.eq(~bus.sel[2])]), # Write/Read data byte: 2 clk
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(2, [rwds.o.eq(~bus.sel[3])]), # Write/Read data byte: 2 clk
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(2, [cs.eq(0), rwds.oe.eq(0), dq.oe.eq(0)]),
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(1, [bus.ack.eq(1)]),
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(1, [bus.ack.eq(0)]),
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(0, []),
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]
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# Convert delta-time sequencer to time sequencer
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t_seq = []
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t_seq_start = (clk_phase == 1)
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t = 0
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for dt, a in dt_seq:
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t_seq.append((t, a))
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t += dt
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self.sync += timeline(bus.cyc & bus.stb & t_seq_start, t_seq)
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def add_tristate(self, pad):
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t = TSTriple(len(pad))
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self.specials += t.get_tristate(pad)
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return t
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@ -0,0 +1,83 @@
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import unittest
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from migen import *
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from litex.soc.cores.hyperbus import HyperRAM
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def c2bool(c):
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return {"-": 1, "_": 0}[c]
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class Pads: pass
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class HyperRamPads:
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def __init__(self):
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self.clk = Signal()
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self.cs_n = Signal()
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self.dq = Record([("oe", 1), ("o", 8), ("i", 8)])
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self.rwds = Record([("oe", 1), ("o", 1), ("i", 1)])
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class TestHyperBus(unittest.TestCase):
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def test_hyperram_syntax(self):
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pads = Record([("clk", 1), ("cs_n", 1), ("dq", 8), ("rwds", 1)])
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hyperram = HyperRAM(pads)
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pads = Record([("clk_p", 1), ("clk_n", 1), ("cs_n", 1), ("dq", 8), ("rwds", 1)])
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hyperram = HyperRAM(pads)
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def test_hyperram_write(self):
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def fpga_gen(dut):
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yield from dut.bus.write(0x1234, 0xdeadbeef)
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yield
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "--________________________________________________________________------"
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dq_oe = "__------------____________________________________________--------______"
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dq_o = "002000048d000000000000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "__________________________________________________________--------______"
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rwds_o = "________________________________________________________________________"
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for i in range(3):
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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dut = HyperRAM(HyperRamPads())
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)])
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def test_hyperram_read(self):
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def fpga_gen(dut):
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dat = yield from dut.bus.read(0x1234)
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self.assertEqual(dat, 0xdeadbeef)
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "--________________________________________________________________------"
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dq_oe = "__------------__________________________________________________________"
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dq_o = "00a000048d00000000000000000000000000000000000000000000000000000000000000"
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dq_i = "0000000000000000000000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "________________________________________________________________________"
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for i in range(3):
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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yield
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dut = HyperRAM(HyperRamPads())
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)])
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