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https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
build/lattice/prjtrellis: simplify code, remove some workarounds
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parent
a73d9d96b1
commit
49dab3b448
2 changed files with 59 additions and 53 deletions
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@ -16,7 +16,7 @@ class BaseSoC(Module):
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led0_pads = platform.request("user_led", 0)
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led1_pads = platform.request("user_led", 1)
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# no constraint file for now with prjtrellis
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# FIXME: no constraint file for now with prjtrellis
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platform.lookup_request("clk100").attr.add(("LOC", "P3"))
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platform.lookup_request("clk100").attr.add(("IO_TYPE", "LVDS"))
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platform.lookup_request("user_dip_btn").attr.add(("LOC", "H2"))
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@ -26,7 +26,7 @@ class BaseSoC(Module):
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platform.lookup_request("user_led", 1).attr.add(("LOC", "D17"))
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platform.lookup_request("user_led", 1).attr.add(("IO_TYPE", "LVCMOS25"))
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# add TRELLIS_IO instance on all inputs/outputs
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# FIXME: add TRELLIS_IO instance on all inputs/outputs
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sys_clk_pads_i = Signal()
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btn_pads_i = Signal()
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led0_pads_i = Signal()
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@ -53,7 +53,7 @@ class BaseSoC(Module):
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def main():
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platform = versaecp55g.Platform(toolchain="prjtrellis")
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soc = BaseSoC(platform)
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platform.build(soc)
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platform.build(soc, toolchain_path="/home/florent/dev/symbiflow/prjtrellis") # FIXME
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if __name__ == "__main__":
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@ -2,7 +2,6 @@
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# License: BSD
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import os
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import sys
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import subprocess
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from migen.fhdl.structure import _Fragment
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@ -12,19 +11,17 @@ from litex.build import tools
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from litex.build.lattice import common
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def _build_script(source, build_template, build_name, device, basecfg):
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build_script_contents = "# Autogenerated by LiteX\nset -e\n"
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for s in build_template:
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build_script_contents += s.format(build_name=build_name, device=device, basecfg=basecfg) + '\n'
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build_script_file = "build_" + build_name + ".sh"
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tools.write_to_file(build_script_file, build_script_contents)
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return build_script_file
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def _run_script(script):
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r = subprocess.call(["bash", script])
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if r != 0:
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raise OSError("Subprocess failed")
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nextpnr_ecp5_architectures = {
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"lfe5u-25f": "25k",
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"lfe5u-45f": "45k",
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"lfe5u-85f": "85k",
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"lfe5um-25f": "um-25k",
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"lfe5um-45f": "um-45k",
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"lfe5um-85f": "um-85k",
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"lfe5um5g-25f": "um5g-25k",
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"lfe5um5g-45f": "um5g-45k",
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"lfe5um5g-85f": "um5g-85k",
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}
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class LatticePrjTrellisToolchain:
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@ -43,25 +40,13 @@ class LatticePrjTrellisToolchain:
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special_overrides = common.lattice_ecpx_special_overrides
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def __init__(self):
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self.nextpnr_yosys_template = [
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"{read_files}",
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"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
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"synth_ecp5 -nomux -json {build_name}.json -top {build_name}",
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]
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self.nextpnr_build_template = [
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"yosys -q -l {build_name}.rpt {build_name}.ys",
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"nextpnr-ecp5 --json {build_name}.json --textcfg {build_name}.config --basecfg {basecfg} --{device}",
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"ecppack {build_name}.config {build_name}.bit"
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]
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def build(self, platform, fragment, build_dir="build", build_name="top",
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toolchain_path=None, run=True):
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os.makedirs(build_dir, exist_ok=True)
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cwd = os.getcwd()
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os.chdir(build_dir)
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# generate verilog
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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@ -70,36 +55,57 @@ class LatticePrjTrellisToolchain:
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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platform.add_source(v_file)
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yosys_template = self.nextpnr_yosys_template
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ys_contents = "\n".join(_.format(build_name=build_name,
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read_files=self.gen_read_files(platform, v_file))
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for _ in yosys_template)
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# generate yosys script
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def yosys_import_sources(platform):
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includes = ""
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reads = []
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for path in platform.verilog_include_paths:
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includes += " -I" + path
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for filename, language, library in platform.sources:
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reads.append("read_{}{} {}".format(
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language, includes, filename))
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return "\n".join(reads)
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ys_name = build_name + ".ys"
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tools.write_to_file(ys_name, ys_contents)
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yosys_script_file = build_name + ".ys"
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yosys_script_contents = [
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yosys_import_sources(platform),
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"synth_ecp5 -nomux -json {build_name}.json -top {build_name}"
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]
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yosys_script_contents = "\n".join(yosys_script_contents)
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yosys_script_contents = yosys_script_contents.format(build_name=build_name)
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tools.write_to_file(yosys_script_file, yosys_script_contents)
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build_template = self.nextpnr_build_template
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script = _build_script(False, build_template, build_name,
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"um5g-45k", # FIXME
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"../../../../../../../symbiflow/prjtrellis/misc/basecfgs/empty_lfe5um5g-45f.config") # FIXME
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_run_script(script)
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# transform platform.device to nextpnr's architecture / basecfg
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(family, size, package) = platform.device.split("-")
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architecture = nextpnr_ecp5_architectures[(family + "-" + size).lower()]
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basecfg = "empty_" + (family + "-" + size).lower() + ".config"
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basecfg = os.path.join(toolchain_path, "misc", "basecfgs", basecfg)
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# generate build script
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build_script_file = "build_" + build_name + ".sh"
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build_script_contents = [
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"yosys -q -l {build_name}.rpt {build_name}.ys",
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"nextpnr-ecp5 --json {build_name}.json --textcfg {build_name}.config --basecfg {basecfg} --{architecture}",
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"ecppack {build_name}.config {build_name}.bit"
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]
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build_script_contents = "\n".join(build_script_contents)
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build_script_contents = build_script_contents.format(
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build_name=build_name,
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architecture=architecture,
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basecfg=basecfg)
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tools.write_to_file(build_script_file, build_script_contents)
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# run scripts
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if run:
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if subprocess.call(["bash", build_script_file]) != 0:
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raise OSError("Subprocess failed")
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os.chdir(cwd)
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return v_output.ns
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def gen_read_files(self, platform, main):
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sources = platform.sources + [(main, "verilog", "work")]
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incflags = ""
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read_files = list()
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for path in platform.verilog_include_paths:
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incflags += " -I" + path
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for filename, language, library in sources:
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read_files.append("read_{}{} {}".format(language,
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incflags,
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filename))
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return "\n".join(read_files)
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def add_period_constraint(self, platform, clk, period):
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print("TODO: add_period_constraint")
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