Clean up

README

@@ -7,5 +7,15 @@ or external signals.
 [> Status:
 Early development phase
 
+Simulation:
+-tb_spi2Csr      :   Test Spi <--> Csr Bridge : [Ok]
+-tb_TriggerCsr   :   Test Trigger with Csr    : [Ok]
+-tb_RecorderCsr  :   Test Recorder with Csr   : [Ok]
+-tb_MigScope     :   Global Test with Csr     : [Ok]
+
+Example Design:
+-de0_nano        :   Generate Signals in FPGA and probe them with migScope : [Wip]
+
+
 [> Contact
 E-mail: florent@enjoy-digital.fr

examples/de0_nano/top.py

@@ -11,13 +11,13 @@
 #                  ----------------------------------
 ################################################################################
 #
-# In this example, signals are generated inside generated inside the FPGA. 
+# In this example signals are generated in the FPGA. 
-# We will use migScope to record those signals it and visualize them.
+# We will use migScope to record those signals and visualize them.
 # 
 # Example architecture:
 # ----------------------
-#        migScope Config  <-- Python Client (Host) --> Vcd Output
+#        migScope Config  --> Python Client (Host) --> Vcd Output
-#                                   |
+#             & Trig                |
 #                        Arduino (Uart<-->Spi Bridge)
 #                                   |
 #                                De0 Nano

sim/tb_TriggerCsr.py

@@ -16,7 +16,6 @@ def term_prog(off, dat):
 	for i in range(4):
 		yield TWrite(off+3-i, (dat>>(8*i))&0xFF)
 
-
 def sum_prog(off, addr, dat):
 	we = 2
 	yield TWrite(off+3, addr%0xFF)

sim/tb_spi2Csr.py

@@ -134,7 +134,6 @@ class SpiMaster(PureSimulable):
 					self.transaction_cnt +=1
 
 
-
 def main():
 	# Csr Slave
 	scratch_reg0 = RegisterField("scratch_reg0", 32, reset=0, access_dev=READ_ONLY)