Clean up

README

@@ -7,5 +7,15 @@ or external signals.
 [> Status:
 Early development phase
 
+Simulation:
+-tb_spi2Csr      :   Test Spi <--> Csr Bridge : [Ok]
+-tb_TriggerCsr   :   Test Trigger with Csr    : [Ok]
+-tb_RecorderCsr  :   Test Recorder with Csr   : [Ok]
+-tb_MigScope     :   Global Test with Csr     : [Ok]
+
+Example Design:
+-de0_nano        :   Generate Signals in FPGA and probe them with migScope : [Wip]
+
+
 [> Contact
 E-mail: florent@enjoy-digital.fr

examples/de0_nano/top.py

@@ -11,13 +11,13 @@
 #                  ----------------------------------
 ################################################################################
 #
-# In this example, signals are generated inside generated inside the FPGA. 
+# In this example signals are generated in the FPGA. 
-# We will use migScope to record those signals it and visualize them.
+# We will use migScope to record those signals and visualize them.
 # 
 # Example architecture:
 # ----------------------
-#        migScope Config  <-- Python Client (Host) --> Vcd Output
+#        migScope Config  --> Python Client (Host) --> Vcd Output
-#                                   |
+#             & Trig                |
 #                        Arduino (Uart<-->Spi Bridge)
 #                                   |
 #                                De0 Nano

migScope/recorder.py

@@ -135,7 +135,7 @@ class Recorder:
 		self._offset = RegisterField("offset", self.depth_width, reset=1)
 		
 		self._get = RegisterField("get", reset=0)
-		self._get_dat = RegisterField("get_dat", self.width, reset=1,access_bus=READ_ONLY, access_dev=WRITE_ONLY)
+		self._get_dat = RegisterField("get_dat", self.width, reset=1, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
 		
 		regs = [self._rst, self._arm, self._done,
 			self._size, self._offset,

migScope/tools/conv.py

@@ -1,4 +1,4 @@
-def dec2bin(d,nb=0):
+def dec2bin(d, nb=0):
 	if d=="x":
 		return "x"*nb
 	elif d==0:

migScope/tools/truthtable.py

@@ -3,7 +3,7 @@ import re
 import sys
 
 def get_operands(s):
-	return sorted(re.findall("[A-z0-9_]+",s))
+	return sorted(re.findall("[A-z0-9_]+", s))
 
 def gen_truth_table(s):
 	operands = get_operands(s)

migScope/tools/vcd.py

@@ -24,7 +24,7 @@ class Var:
 		try : 
 			if self.values[cnt+1] != self.val:
 				r += "b"
-				r += dec2bin(self.values[cnt+1],self.width)
+				r += dec2bin(self.values[cnt+1], self.width)
 				r += " "
 				r += self.vcd_id
 				r += "\n"
@@ -158,12 +158,12 @@ class Vcd:
 
 def main():
 	myvcd = Vcd()
-	myvcd.add(Var("wire",1,"foo1",[0,1,0,1,0,1]))
+	myvcd.add(Var("wire", 1, "foo1", [0,1,0,1,0,1]))
-	myvcd.add(Var("wire",2,"foo2",[1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
+	myvcd.add(Var("wire", 2, "foo2", [1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
-	myvcd.add(Var("wire",3,"foo3"))
+	myvcd.add(Var("wire", 3, "foo3"))
-	myvcd.add(Var("wire",4,"foo4"))
+	myvcd.add(Var("wire", 4, "foo4"))
 	ramp = [i%128 for i in range(1024)]
-	myvcd.add(Var("wire",16,"ramp",ramp))
+	myvcd.add(Var("wire", 16, "ramp", ramp))
 	print(myvcd)
 	
 if __name__ == '__main__':

migScope/trigger.py

@@ -209,7 +209,7 @@ class Sum:
 			sync += [self.o.eq(self._o)]
 		else:
 			comb += [self.o.eq(self._o)]
-		return Fragment(comb=comb,sync=sync,memories=memories)
+		return Fragment(comb=comb, sync=sync, memories=memories)
 		
 	def connect_to_reg(self, reg):
 		comb = []
@@ -242,7 +242,7 @@ class Trigger:
 		for port in self.ports:
 			setattr(self,port.reg_name,RegisterField(port.reg_name, port.reg_size, reset=0,
 				access_bus=WRITE_ONLY, access_dev=READ_ONLY))
-		self.sum_reg = RegisterField(self.sum.reg_name, self.sum.reg_size, reset=0,access_bus=WRITE_ONLY, access_dev=READ_ONLY)
+		self.sum_reg = RegisterField(self.sum.reg_name, self.sum.reg_size, reset=0, access_bus=WRITE_ONLY, access_dev=READ_ONLY)
 		
 		regs = []
 		objects = self.__dict__

sim/tb_Migscope.py

@@ -41,10 +41,10 @@ def csr_transactions(trigger0, recorder0):
 
 	# Term Prog
 	term_trans = []
-	term_trans += [term_prog(trigger0.ports[0].reg_base,0x00000000)]
+	term_trans += [term_prog(trigger0.ports[0].reg_base, 0x00000000)]
-	term_trans += [term_prog(trigger0.ports[1].reg_base,0x00000004)]
+	term_trans += [term_prog(trigger0.ports[1].reg_base, 0x00000004)]
-	term_trans += [term_prog(trigger0.ports[2].reg_base,0x00000008)]
+	term_trans += [term_prog(trigger0.ports[2].reg_base, 0x00000008)]
-	term_trans += [term_prog(trigger0.ports[3].reg_base,0x0000000C)]
+	term_trans += [term_prog(trigger0.ports[3].reg_base, 0x0000000C)]
 	for t in term_trans:
 		for r in t:
 			yield r
@@ -53,7 +53,7 @@ def csr_transactions(trigger0, recorder0):
 	sum_tt = gen_truth_table("term0 | term1 | term2 | term3")
 	sum_trans = []
 	for i in range(len(sum_tt)):
-		sum_trans.append(sum_prog(trigger0.sum.reg_base,i,sum_tt[i]))
+		sum_trans.append(sum_prog(trigger0.sum.reg_base, i, sum_tt[i]))
 	for t in sum_trans:
 		for r in t:
 			yield r
@@ -159,8 +159,8 @@ def main():
 	def end_simulation(s):
 		s.interrupt = csr_master0.done
 		myvcd = Vcd()
-		myvcd.add(Var("wire",32,"trig_dat",dat_vcd))
+		myvcd.add(Var("wire", 32, "trig_dat", dat_vcd))
-		f = open("tb_Miscope_Out.vcd","w")
+		f = open("tb_Miscope_Out.vcd", "w")
 		f.write(str(myvcd))
 		f.close()
 	

sim/tb_RecorderCsr.py

@@ -66,7 +66,7 @@ def main():
 	csr_master0 = csr.Initiator(csr_transactions())
 
 	# Recorder
-	recorder0 = recorder.Recorder(0,32,1024)
+	recorder0 = recorder.Recorder(0, 32, 1024)
 	
 	# Csr Interconnect
 	csrcon0 = csr.Interconnect(csr_master0.bus,
@@ -78,7 +78,7 @@ def main():
 	def recorder_data(s):
 		global arm_done
 		if arm_done:
-			s.wr(recorder0.trig_hit,1)
+			s.wr(recorder0.trig_hit, 1)
 			arm_done = False
 
 		global trig_dat
@@ -100,7 +100,7 @@ def main():
 	fragment = autofragment.from_local()
 	fragment += Fragment(sim=[end_simulation])
 	fragment += Fragment(sim=[recorder_data])
-	sim = Simulator(fragment, Runner(),TopLevel("tb_RecorderCsr.vcd"))
+	sim = Simulator(fragment, Runner(), TopLevel("tb_RecorderCsr.vcd"))
 	sim.run(10000)
 
 main()

sim/tb_TriggerCsr.py

@@ -16,7 +16,6 @@ def term_prog(off, dat):
 	for i in range(4):
 		yield TWrite(off+3-i, (dat>>(8*i))&0xFF)
 
-
 def sum_prog(off, addr, dat):
 	we = 2
 	yield TWrite(off+3, addr%0xFF)
@@ -41,8 +40,8 @@ def csr_transactions():
 			yield r
 	
 	sum_trans = []
-	sum_trans += [sum_prog(0x00,i,1) for i in range(8)]
+	sum_trans += [sum_prog(0x00, i, 1) for i in range(8)]
-	sum_trans += [sum_prog(0x00,i,0) for i in range(8)]
+	sum_trans += [sum_prog(0x00, i, 0) for i in range(8)]
 	for t in sum_trans:
 		for r in t:
 			yield r
@@ -50,7 +49,7 @@ def csr_transactions():
 	sum_tt = gen_truth_table("i1 & i2 & i3 & i4")
 	sum_trans = []
 	for i in range(len(sum_tt)):
-		sum_trans.append(sum_prog(0x00,i,sum_tt[i]))
+		sum_trans.append(sum_prog(0x00, i, sum_tt[i]))
 	print(sum_tt)
 	for t in sum_trans:
 		for r in t:
@@ -83,10 +82,10 @@ def main():
 	# Term Test
 	def term_stimuli(s):
 		if csr_done:
-			s.wr(term0.i,0xDEADBEEF)
+			s.wr(term0.i, 0xDEADBEEF)
-			s.wr(term1.i,0xCAFEFADE)
+			s.wr(term1.i ,0xCAFEFADE)
-			s.wr(term2.i,0xDEADBEEF)
+			s.wr(term2.i, 0xDEADBEEF)
-			s.wr(term3.i,0xCAFEFADE)
+			s.wr(term3.i, 0xCAFEFADE)
 	
 	
 	# Simulation
@@ -96,7 +95,7 @@ def main():
 	fragment = autofragment.from_local()
 	fragment += Fragment(sim=[end_simulation])
 	fragment += Fragment(sim=[term_stimuli])
-	sim = Simulator(fragment, Runner(),TopLevel("tb_TriggerCsr.vcd"))
+	sim = Simulator(fragment, Runner(), TopLevel("tb_TriggerCsr.vcd"))
 	sim.run(2000)
 
 main()

sim/tb_spi2Csr.py

@@ -134,7 +134,6 @@ class SpiMaster(PureSimulable):
 					self.transaction_cnt +=1
 
 
-
 def main():
 	# Csr Slave
 	scratch_reg0 = RegisterField("scratch_reg0", 32, reset=0, access_dev=READ_ONLY)