build/soc/cpu parser: Improve titles.

litex/build/lattice/icestorm.py

@@ -218,7 +218,7 @@ class LatticeIceStormToolchain:
         self.clocks[clk] = period
 
 def icestorm_args(parser):
-    toolchain_group = parser.add_argument_group("toolchain")
+    toolchain_group = parser.add_argument_group(title="Toolchain options")
     toolchain_group.add_argument("--nextpnr-timingstrict", action="store_true", help="Make the build fail when Timing is not met.")
     toolchain_group.add_argument("--nextpnr-ignoreloops",  action="store_true", help="Use strict Timing mode (Build will fail when Timings are not met).")
     toolchain_group.add_argument("--nextpnr-seed",         default=1, type=int, help="Set Nextpnr's seed.")

litex/build/lattice/oxide.py

@@ -189,7 +189,7 @@ class LatticeOxideToolchain:
             self.false_paths.add((from_, to))
 
 def oxide_args(parser):
-    toolchain_group = parser.add_argument_group("toolchain")
+    toolchain_group = parser.add_argument_group(title="Toolchain options")
     toolchain_group.add_argument("--yosys-nowidelut",      action="store_true", help="Use Yosys's nowidelut mode.")
     toolchain_group.add_argument("--yosys-abc9",           action="store_true", help="Use Yosys's abc9 mode.")
     toolchain_group.add_argument("--nextpnr-timingstrict", action="store_true", help="Use strict Timing mode (Build will fail when Timings are not met).")

litex/build/lattice/radiant.py

@@ -320,7 +320,7 @@ class LatticeRadiantToolchain:
             self.false_paths.add((from_, to))
 
 def radiant_build_args(parser):
-    toolchain_group = parser.add_argument_group("toolchain")
+    toolchain_group = parser.add_argument_group(title="Toolchain options")
     toolchain_group.add_argument("--synth-mode", default="synplify", help="Synthesis mode (synplify or yosys).")
 
 def radiant_build_argdict(args):

litex/build/lattice/trellis.py

@@ -250,7 +250,7 @@ class LatticeTrellisToolchain:
             self.false_paths.add((from_, to))
 
 def trellis_args(parser):
-    toolchain_group = parser.add_argument_group("toolchain")
+    toolchain_group = parser.add_argument_group(title="Toolchain options")
     toolchain_group.add_argument("--yosys-nowidelut",      action="store_true", help="Use Yosys's nowidelut mode.")
     toolchain_group.add_argument("--yosys-abc9",           action="store_true", help="Use Yosys's abc9 mode.")
     toolchain_group.add_argument("--nextpnr-timingstrict", action="store_true", help="Use strict Timing mode (Build will fail when Timings are not met).")

litex/build/sim/verilator.py

@@ -261,7 +261,7 @@ class SimVerilatorToolchain:
             return v_output.ns
 
 def verilator_build_args(parser):
-    toolchain_group = parser.add_argument_group("toolchain")
+    toolchain_group = parser.add_argument_group(title="Toolchain options")
     toolchain_group.add_argument("--threads",      default=1,           help="Set number of threads.")
     toolchain_group.add_argument("--trace",        action="store_true", help="Enable Tracing.")
     toolchain_group.add_argument("--trace-fst",    action="store_true", help="Enable FST tracing.")

litex/build/xilinx/vivado.py

@@ -391,7 +391,7 @@ class XilinxVivadoToolchain:
             self.false_paths.add((from_, to))
 
 def vivado_build_args(parser):
-    toolchain_group = parser.add_argument_group("toolchain")
+    toolchain_group = parser.add_argument_group(title="Toolchain options")
     toolchain_group.add_argument("--synth-mode", default="vivado", help="Synthesis mode (vivado or yosys).")
 
 def vivado_build_argdict(args):

litex/soc/cores/cpu/naxriscv/core.py

@@ -91,7 +91,7 @@ class NaxRiscv(CPU):
     # Command line configuration arguments.
     @staticmethod
     def args_fill(parser):
-        cpu_group = parser.add_argument_group("cpu")
+        cpu_group = parser.add_argument_group(title="CPU options")
         cpu_group.add_argument("--scala-file", action="append", help="Specify the scala files used to configure NaxRiscv.")
         cpu_group.add_argument("--xlen",       default=32,      help="Specify the RISC-V data width.")
 

litex/soc/cores/cpu/vexriscv_smp/core.py

@@ -63,7 +63,7 @@ class VexRiscvSMP(CPU):
     # Command line configuration arguments.
     @staticmethod
     def args_fill(parser):
-        cpu_group = parser.add_argument_group("cpu")
+        cpu_group = parser.add_argument_group(title="CPU options")
         cpu_group.add_argument("--cpu-count",                    default=1,           help="Number of CPU(s) in the cluster.", type=int)
         cpu_group.add_argument("--with-coherent-dma",            action="store_true", help="Enable Coherent DMA Slave interface.")
         cpu_group.add_argument("--without-coherent-dma",         action="store_true", help="Disable Coherent DMA Slave interface.")

litex/soc/integration/builder.py

@@ -375,7 +375,7 @@ class Builder:
 
 def builder_args(parser):
     parser.formatter_class = lambda prog: argparse.ArgumentDefaultsHelpFormatter(prog, max_help_position=10, width=120)
-    builder_group = parser.add_argument_group("builder")
+    builder_group = parser.add_argument_group("Builder options")
     builder_group.add_argument("--output-dir",          default=None,        help="Base Output directory.")
     builder_group.add_argument("--gateware-dir",        default=None,        help="Output directory for Gateware files.")
     builder_group.add_argument("--software-dir",        default=None,        help="Output directory for Software files.")

litex/soc/integration/soc_core.py

@@ -295,7 +295,7 @@ class SoCCore(LiteXSoC):
 # SoCCore arguments --------------------------------------------------------------------------------
 
 def soc_core_args(parser):
-    soc_group = parser.add_argument_group("soc")
+    soc_group = parser.add_argument_group("SoC options")
     # Bus parameters
     soc_group.add_argument("--bus-standard",      default="wishbone",                help="Select bus standard: {}.".format(", ".join(SoCBusHandler.supported_standard)))
     soc_group.add_argument("--bus-data-width",    default=32,         type=auto_int, help="Bus data-width.")