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sdram/module: cleanup indent

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This commit is contained in:
Florent Kermarrec 2015-08-20 22:15:06 +02:00
parent 63538a7d04
commit 4acab79987
1 changed files with 63 additions and 63 deletions
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126
misoclib/mem/sdram/module.py
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@ -48,18 +48,18 @@ class SDRAMModule:
# SDR # SDR
class IS42S16160(SDRAMModule): class IS42S16160(SDRAMModule):
geom_settings = { geom_settings = {
"nbanks": 4, "nbanks": 4,
"nrows": 8192, "nrows": 8192,
"ncols": 512 "ncols": 512
} }
# Note: timings for -7 speedgrade (add support for others speedgrades) # Note: timings for -7 speedgrade (add support for others speedgrades)
timing_settings = { timing_settings = {
"tRP": 20, "tRP": 20,
"tRCD": 20, "tRCD": 20,
"tWR": 20, "tWR": 20,
"tWTR": 2, "tWTR": 2,
"tREFI": 64*1000*1000/8192, "tREFI": 64*1000*1000/8192,
"tRFC": 70 "tRFC": 70
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings, SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
@ -68,17 +68,17 @@ class IS42S16160(SDRAMModule):
class MT48LC4M16(SDRAMModule): class MT48LC4M16(SDRAMModule):
geom_settings = { geom_settings = {
"nbanks": 4, "nbanks": 4,
"nrows": 4096, "nrows": 4096,
"ncols": 256 "ncols": 256
} }
timing_settings = { timing_settings = {
"tRP": 15, "tRP": 15,
"tRCD": 15, "tRCD": 15,
"tWR": 14, "tWR": 14,
"tWTR": 2, "tWTR": 2,
"tREFI": 64*1000*1000/4096, "tREFI": 64*1000*1000/4096,
"tRFC": 66 "tRFC": 66
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings, SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
@ -87,18 +87,18 @@ class MT48LC4M16(SDRAMModule):
class AS4C16M16(SDRAMModule): class AS4C16M16(SDRAMModule):
geom_settings = { geom_settings = {
"nbanks": 4, "nbanks": 4,
"nrows": 8192, "nrows": 8192,
"ncols": 512 "ncols": 512
} }
# Note: timings for -6 speedgrade (add support for others speedgrades) # Note: timings for -6 speedgrade (add support for others speedgrades)
timing_settings = { timing_settings = {
"tRP": 18, "tRP": 18,
"tRCD": 18, "tRCD": 18,
"tWR": 12, "tWR": 12,
"tWTR": 2, "tWTR": 2,
"tREFI": 64*1000*1000/8192, "tREFI": 64*1000*1000/8192,
"tRFC": 60 "tRFC": 60
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings, SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
@ -108,17 +108,17 @@ class AS4C16M16(SDRAMModule):
# DDR # DDR
class MT46V32M16(SDRAMModule): class MT46V32M16(SDRAMModule):
geom_settings = { geom_settings = {
"nbanks": 4, "nbanks": 4,
"nrows": 8192, "nrows": 8192,
"ncols": 1024 "ncols": 1024
} }
timing_settings = { timing_settings = {
"tRP": 15, "tRP": 15,
"tRCD": 15, "tRCD": 15,
"tWR": 15, "tWR": 15,
"tWTR": 2, "tWTR": 2,
"tREFI": 64*1000*1000/8192, "tREFI": 64*1000*1000/8192,
"tRFC": 70 "tRFC": 70
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR", self.geom_settings, SDRAMModule.__init__(self, clk_freq, "DDR", self.geom_settings,
@ -128,17 +128,17 @@ class MT46V32M16(SDRAMModule):
# LPDDR # LPDDR
class MT46H32M16(SDRAMModule): class MT46H32M16(SDRAMModule):
geom_settings = { geom_settings = {
"nbanks": 4, "nbanks": 4,
"nrows": 8192, "nrows": 8192,
"ncols": 1024 "ncols": 1024
} }
timing_settings = { timing_settings = {
"tRP": 15, "tRP": 15,
"tRCD": 15, "tRCD": 15,
"tWR": 15, "tWR": 15,
"tWTR": 2, "tWTR": 2,
"tREFI": 64*1000*1000/8192, "tREFI": 64*1000*1000/8192,
"tRFC": 72 "tRFC": 72
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "LPDDR", self.geom_settings, SDRAMModule.__init__(self, clk_freq, "LPDDR", self.geom_settings,
@ -148,17 +148,17 @@ class MT46H32M16(SDRAMModule):
# DDR2 # DDR2
class MT47H128M8(SDRAMModule): class MT47H128M8(SDRAMModule):
geom_settings = { geom_settings = {
"nbanks": 8, "nbanks": 8,
"nrows": 16384, "nrows": 16384,
"ncols": 1024 "ncols": 1024
} }
timing_settings = { timing_settings = {
"tRP": 15, "tRP": 15,
"tRCD": 15, "tRCD": 15,
"tWR": 15, "tWR": 15,
"tWTR": 2, "tWTR": 2,
"tREFI": 7800, "tREFI": 7800,
"tRFC": 127.5 "tRFC": 127.5
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings, SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
@ -168,17 +168,17 @@ class MT47H128M8(SDRAMModule):
# DDR3 # DDR3
class MT8JTF12864(SDRAMModule): class MT8JTF12864(SDRAMModule):
geom_settings = { geom_settings = {
"nbanks": 8, "nbanks": 8,
"nrows": 16384, "nrows": 16384,
"ncols": 1024 "ncols": 1024
} }
timing_settings = { timing_settings = {
"tRP": 15, "tRP": 15,
"tRCD": 15, "tRCD": 15,
"tWR": 15, "tWR": 15,
"tWTR": 2, "tWTR": 2,
"tREFI": 7800, "tREFI": 7800,
"tRFC": 70 "tRFC": 70
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings, SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,