build/osfpga: Add fake OSFPGAAsyncResetSynchronizer and false_path_constraint to be able to generate more cores.

Code will be replaced when information will be available.

litex/build/osfpga/common.py

@@ -9,6 +9,19 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.build.io import *
 
-# OS-FPGA Special Overrides ------------------------------------------------------------------------
+# OS-FPGA AsyncResetSynchronizer -------------------------------------------------------------------
 
-osfpga_special_overrides = {}
+class OSFPGAAsyncResetSynchronizerImpl(Module):
+    def __init__(self, cd, async_reset):
+        self.comb += cd.rst.eq(async_reset) # FIXME: Implement.
+
+class OSFPGAAsyncResetSynchronizer:
+    @staticmethod
+    def lower(dr):
+        return OSFPGAAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
+
+# OS-FPGA Special Overrides -------------------------------------------------------------------------
+
+osfpga_special_overrides = {
+    AsyncResetSynchronizer: OSFPGAAsyncResetSynchronizer,
+}

litex/build/osfpga/platform.py

@@ -38,3 +38,6 @@ class OSFPGAPlatform(GenericPlatform):
     def add_period_constraint(self, clk, period):
         if clk is None: return
         self.toolchain.add_period_constraint(self, clk, period)
+
+    def add_false_path_constraint(self, from_, to):
+        pass # FIXME: Implement.