integration/soc: add add_sdcard method with integration code from nexys4ddr.
Even if not cleaned up yet, having it there will avoid duplications in targets.
This commit is contained in:
Florent Kermarrec
parent
c78caeb998
commit
4b3afa75a7
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@ -21,14 +21,6 @@ from litedram.phy import s7ddrphy
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from liteeth.phy.rmii import LiteEthPHYRMII
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from liteeth.phy.rmii import LiteEthPHYRMII
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from litesdcard.phy import SDPHY
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from litesdcard.clocker import SDClockerS7
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from litesdcard.core import SDCore
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from litesdcard.bist import BISTBlockGenerator, BISTBlockChecker
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from litesdcard.data import SDDataReader, SDDataWriter
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from litex.soc.cores.timer import Timer
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from litex.soc.interconnect import wishbone
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# CRG ----------------------------------------------------------------------------------------------
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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class _CRG(Module):
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@ -99,56 +91,6 @@ class BaseSoC(SoCCore):
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sys_clk_freq = sys_clk_freq)
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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self.add_csr("leds")
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def add_sdcard(self, memory_size=512, memory_width=32):
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sdcard_pads = self.platform.request("sdcard")
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if hasattr(sdcard_pads, "rst"):
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self.comb += sdcard_pads.rst.eq(0)
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self.submodules.sdclk = SDClockerS7(sys_clk_freq=self.sys_clk_freq)
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self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device)
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self.submodules.sdcore = SDCore(self.sdphy, csr_data_width=self.csr_data_width)
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self.submodules.sdtimer = Timer()
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self.add_csr("sdclk")
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self.add_csr("sdphy")
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self.add_csr("sdcore")
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self.add_csr("sdtimer")
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# SD Card data reader
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sdread_mem = Memory(memory_width, memory_size//4)
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sdread_sram = FullMemoryWE()(wishbone.SRAM(sdread_mem, read_only=True))
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self.submodules += sdread_sram
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self.add_wb_slave(self.mem_map["sdread"], sdread_sram.bus, memory_size)
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self.add_memory_region("sdread", self.mem_map["sdread"], memory_size)
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sdread_port = sdread_sram.mem.get_port(write_capable=True);
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self.specials += sdread_port
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self.submodules.sddatareader = SDDataReader(port=sdread_port, endianness=self.cpu.endianness)
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self.add_csr("sddatareader")
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self.comb += self.sdcore.source.connect(self.sddatareader.sink),
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# SD Card data writer
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sdwrite_mem = Memory(memory_width, memory_size//4)
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sdwrite_sram = FullMemoryWE()(wishbone.SRAM(sdwrite_mem, read_only=False))
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self.submodules += sdwrite_sram
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self.add_wb_slave(self.mem_map["sdwrite"], sdwrite_sram.bus, memory_size)
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self.add_memory_region("sdwrite", self.mem_map["sdwrite"], memory_size)
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sdwrite_port = sdwrite_sram.mem.get_port(write_capable=False, async_read=True, mode=READ_FIRST);
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self.specials += sdwrite_port
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self.submodules.sddatawriter = SDDataWriter(port=sdwrite_port, endianness=self.cpu.endianness)
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self.add_csr("sddatawriter")
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self.comb += self.sddatawriter.source.connect(self.sdcore.sink),
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self.platform.add_period_constraint(self.sdclk.cd_sd.clk, period_ns(self.sys_clk_freq))
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self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, period_ns(self.sys_clk_freq))
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.sdclk.cd_sd.clk,
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self.sdclk.cd_sd_fb.clk)
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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def main():
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def main():
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@ -166,11 +108,10 @@ def main():
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soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
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soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
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with_ethernet=args.with_ethernet,
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with_ethernet=args.with_ethernet,
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**soc_sdram_argdict(args))
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**soc_sdram_argdict(args))
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assert not (args.with_spi_sdcard and args.with_spi_sdcard)
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if args.with_spi_sdcard:
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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soc.add_spi_sdcard()
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if args.with_sdcard:
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if args.with_sdcard:
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if args.with_spi_sdcard:
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raise ValueError("'--with-spi-sdcard' and '--with-sdcard' are mutually exclusive!")
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soc.add_sdcard()
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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builder.build(run=args.build)
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@ -1241,3 +1241,60 @@ class LiteXSoC(SoC):
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spisdcard.add_clk_divider()
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spisdcard.add_clk_divider()
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setattr(self.submodules, name, spisdcard)
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setattr(self.submodules, name, spisdcard)
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self.add_csr(name)
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self.add_csr(name)
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# Add SDCard -----------------------------------------------------------------------------------
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def add_sdcard(self, name="sdcard", memory_size=512, memory_width=32):
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assert self.platform.device[:3] == "xc7" # FIXME: Only supports 7-Series for now.
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# Imports
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from litesdcard.phy import SDPHY
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from litesdcard.clocker import SDClockerS7
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from litesdcard.core import SDCore
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from litesdcard.bist import BISTBlockGenerator, BISTBlockChecker
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from litesdcard.data import SDDataReader, SDDataWriter
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# Core
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sdcard_pads = self.platform.request(name)
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if hasattr(sdcard_pads, "rst"):
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self.comb += sdcard_pads.rst.eq(0)
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self.submodules.sdclk = SDClockerS7(sys_clk_freq=self.sys_clk_freq)
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self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device)
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self.submodules.sdcore = SDCore(self.sdphy, csr_data_width=self.csr_data_width)
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self.submodules.sdtimer = Timer()
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self.add_csr("sdclk")
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self.add_csr("sdphy")
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self.add_csr("sdcore")
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self.add_csr("sdtimer")
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# SD Card Data Reader
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sdread_mem = Memory(memory_width, memory_size//4)
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sdread_sram = FullMemoryWE()(wishbone.SRAM(sdread_mem, read_only=True))
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self.submodules += sdread_sram
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self.add_wb_slave(self.mem_map["sdread"], sdread_sram.bus, memory_size)
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self.add_memory_region("sdread", self.mem_map["sdread"], memory_size)
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sdread_port = sdread_sram.mem.get_port(write_capable=True);
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self.specials += sdread_port
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self.submodules.sddatareader = SDDataReader(port=sdread_port, endianness=self.cpu.endianness)
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self.add_csr("sddatareader")
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self.comb += self.sdcore.source.connect(self.sddatareader.sink),
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# SD Card Data Writer
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sdwrite_mem = Memory(memory_width, memory_size//4)
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sdwrite_sram = FullMemoryWE()(wishbone.SRAM(sdwrite_mem, read_only=False))
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self.submodules += sdwrite_sram
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self.add_wb_slave(self.mem_map["sdwrite"], sdwrite_sram.bus, memory_size)
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self.add_memory_region("sdwrite", self.mem_map["sdwrite"], memory_size)
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sdwrite_port = sdwrite_sram.mem.get_port(write_capable=False, async_read=True, mode=READ_FIRST);
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self.specials += sdwrite_port
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self.submodules.sddatawriter = SDDataWriter(port=sdwrite_port, endianness=self.cpu.endianness)
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self.add_csr("sddatawriter")
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self.comb += self.sddatawriter.source.connect(self.sdcore.sink),
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self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/self.sys_clk_freq)
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self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/self.sys_clk_freq)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.sdclk.cd_sd.clk,
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self.sdclk.cd_sd_fb.clk)
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