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soc/cores/dma: Add default parameters to add_ctrl.

This commit is contained in:
Florent Kermarrec 2024-06-26 17:57:47 +02:00
parent 01a15e4bbf
commit 4b745f9eba
1 changed files with 10 additions and 10 deletions
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20
litex/soc/cores/dma.py
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@ -74,12 +74,12 @@ class WishboneDMAReader(LiteXModule):
self.add_ctrl() self.add_ctrl()
self.add_csr() self.add_csr()
def add_ctrl(self): def add_ctrl(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
self.base = Signal(64) self.base = Signal(64, reset=default_base)
self.length = Signal(32) self.length = Signal(32, reset=default_length)
self.enable = Signal() self.enable = Signal(reset=default_enable)
self.done = Signal() self.done = Signal()
self.loop = Signal() self.loop = Signal(reset=default_loop)
self.offset = Signal(32) self.offset = Signal(32)
# # # # # #
@ -176,15 +176,15 @@ class WishboneDMAWriter(LiteXModule):
self.add_ctrl() self.add_ctrl()
self.add_csr() self.add_csr()
def add_ctrl(self, ready_on_idle=1): def add_ctrl(self, default_base=0, default_length=0, default_enable=0, default_loop=0, ready_on_idle=1):
self._sink = self.sink self._sink = self.sink
self.sink = stream.Endpoint([("data", self.bus.data_width)]) self.sink = stream.Endpoint([("data", self.bus.data_width)])
self.base = Signal(64) self.base = Signal(64, reset=default_base)
self.length = Signal(32) self.length = Signal(32, reset=default_length)
self.enable = Signal() self.enable = Signal(reset=default_enable)
self.done = Signal() self.done = Signal()
self.loop = Signal() self.loop = Signal(reset=default_loop)
self.offset = Signal(32) self.offset = Signal(32)
# # # # # #