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integration/soc/bus_addresing_convert: Simplify and skip on AXI/AXI-Lite interface since already handled in bridges.

This commit is contained in:
Florent Kermarrec 2023-11-09 10:22:22 +01:00
parent 03a0739d13
commit 4b9c866d76
1 changed files with 5 additions and 7 deletions
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12
litex/soc/integration/soc.py
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@ -350,24 +350,22 @@ class SoCBusHandler(LiteXModule):
# Same Addressing, return un-modified interface.
if interface.addressing == self.addressing:
return interface
# AXI/AXI-Lite interface, Bus-Addressing conversion already handled in Bus-Standard conversion.
elif isinstance(interface, (axi.AXIInterface, axi.AXILiteInterface)):
return interface
# Different Addressing: Return adapted interface.
else:
interface_cls = type(interface)
assert interface_cls == wishbone.Interface # FIXME: Remove limitation.
adapted_interface = interface_cls(
data_width = self.data_width,
address_width = self.address_width,
addressing = self.addressing,
)
address_shift = log2_int(interface.data_width//8)
print(adapted_interface)
print(adapted_interface.addressing)
print(address_shift)
self.comb += adapted_interface.connect(interface, omit={"adr"})
if direction == "m2s":
self.comb += interface.connect(adapted_interface, omit={"adr"})
self.comb += adapted_interface.adr.eq(interface.adr[address_shift:])
elif direction == "s2m":
self.comb += adapted_interface.connect(interface, omit={"adr"})
if direction == "s2m":
self.comb += interface.adr.eq(adapted_interface.adr[address_shift:])
return adapted_interface