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bus/wishbone/sram: accept memories < 32 bits

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This commit is contained in:
Sebastien Bourdeauducq 2012-12-01 13:04:22 +01:00
parent 523816982a
commit 4bcb39699b
1 changed files with 1 additions and 1 deletions
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2
migen/bus/wishbone.py
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@ -197,7 +197,7 @@ class Target(PureSimulable):
class SRAM:
def __init__(self, mem_or_size, bus=Interface()):
if isinstance(mem_or_size, Memory):
assert(mem_or_size.width == 32)
assert(mem_or_size.width <= 32)
self.mem = mem_or_size
else:
self.mem = Memory(32, mem_or_size//4)