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litescope: remove repeat mode on drivers (not useful) and cleanup

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This commit is contained in:
Florent Kermarrec 2015-04-18 15:37:38 +02:00
parent 5a930fe7cf
commit 4c0d9f5f36
4 changed files with 58 additions and 69 deletions
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15
misoclib/tools/litescope/host/driver/etherbone.py
View file

@ -23,12 +23,8 @@ class LiteScopeEtherboneDriver:
def close(self):
pass
def read(self, addr, burst_length=None, repeats=None):
def to_int(v):
return 1 if v is None else v
reads_addrs = []
for i in range(to_int(repeats)):
reads_addrs += [addr+4*j for j in range(to_int(burst_length))]
def read(self, addr, burst_length=1):
reads_addrs = [addr+4*j for j in range(burst_length)]
reads = EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs)
record = EtherboneRecord()
record.writes = None
@ -54,8 +50,11 @@ class LiteScopeEtherboneDriver:
datas = packet.records.pop().writes.get_datas()
if self.debug:
for i, data in enumerate(datas):
print("RD {:08X} @ {:08X}".format(data, addr + 4*(i%to_int(burst_length))))
return datas
print("RD {:08X} @ {:08X}".format(data, addr + 4*i))
if burst_length == 1:
return datas[0]
else:
return datas
def write(self, addr, datas):
if not isinstance(datas, list):

17
misoclib/tools/litescope/host/driver/pcie.py
View file

@ -21,10 +21,8 @@ class LiteScopePCIeDriver:
self.mmap.close()
self.f.close()
def read(self, addr, burst_length=None, repeats=None):
if repeats is not None:
raise NotImplementedError
values = []
def read(self, addr, burst_length=1):
datas = []
for i in range(burst_length):
self.mmap.seek(addr + 4*i)
dat = self.mmap.read(4)
@ -34,8 +32,11 @@ class LiteScopePCIeDriver:
val |= dat[0] << 0
if self.debug:
print("RD {:08X} @ {:08X}".format(val, addr + 4*i))
values.append(val)
return values
datas.append(val)
if burst_length == 1:
return datas[0]
else:
return datas
def write(self, addr, data):
if isinstance(data, list):
@ -48,8 +49,8 @@ class LiteScopePCIeDriver:
dat_bytes = [0, 0, 0, 0]
dat_bytes[3] = (dat >> 24) & 0xff
dat_bytes[2] = (dat >> 16) & 0xff
dat_bytes[1] = (dat >> 8) & 0xff
dat_bytes[0] = (dat >> 0) & 0xff
dat_bytes[1] = (dat >> 8) & 0xff
dat_bytes[0] = (dat >> 0) & 0xff
self.mmap[addr + 4*i:addr + 4*(i+1)] = bytes(dat_bytes)
if self.debug:
print("WR {:08X} @ {:08X}".format(dat, (addr + i)*4))

24
misoclib/tools/litescope/host/driver/reg.py
View file

@ -10,24 +10,18 @@ class MappedReg:
self.busword = busword
self.mode = mode
def read(self, repeats=None):
def read(self):
if self.mode not in ["rw", "ro"]:
raise KeyError(name + "register not readable")
def to_int(v):
return 1 if v is None else v
read_datas = self.readfn(self.addr, burst_length=self.length, repeats=repeats)
datas = []
for i in range(to_int(repeats)):
data = 0
for j in range(self.length):
data = data << self.busword
data |= read_datas[i*self.length+j]
datas.append(data)
if repeats is None:
return datas[0]
else:
datas = self.readfn(self.addr, burst_length=self.length)
if isinstance(datas, int):
return datas
else:
data = 0
for i in range(self.length):
data = data << self.busword
data |= read_datas[i]
return data
def write(self, value):
if self.mode not in ["rw", "wo"]:

69
misoclib/tools/litescope/host/driver/uart.py
View file

@ -10,7 +10,7 @@ def write_b(uart, data):
class LiteScopeUARTDriver:
cmds = {
"write": 0x01,
"read": 0x02
"read": 0x02
}
def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False):
self.port = port
@ -38,51 +38,46 @@ class LiteScopeUARTDriver:
self.uart.flushOutput()
self.uart.close()
def read(self, addr, burst_length=None, repeats=None):
def read(self, addr, burst_length=1):
datas = []
def to_int(v):
return 1 if v is None else v
for i in range(to_int(repeats)):
self.uart.flushInput()
write_b(self.uart, self.cmds["read"])
write_b(self.uart, burst_length)
write_b(self.uart, (addr//4 & 0xff000000) >> 24)
write_b(self.uart, (addr//4 & 0x00ff0000) >> 16)
write_b(self.uart, (addr//4 & 0x0000ff00) >> 8)
write_b(self.uart, (addr//4 & 0x000000ff))
for j in range(to_int(burst_length)):
data = 0
for k in range(4):
data = data << 8
data |= ord(self.uart.read())
if self.debug:
print("RD {:08X} @ {:08X}".format(data, (addr+j)*4))
datas.append(data)
return datas
self.uart.flushInput()
write_b(self.uart, self.cmds["read"])
write_b(self.uart, burst_length)
word_addr = addr//4
write_b(self.uart, (word_addr >> 24) & 0xff)
write_b(self.uart, (word_addr >> 16) & 0xff)
write_b(self.uart, (word_addr >> 8) & 0xff)
write_b(self.uart, (word_addr >> 0) & 0xff)
for i in range(burst_length):
data = 0
for k in range(4):
data = data << 8
data |= ord(self.uart.read())
if self.debug:
print("RD {:08X} @ {:08X}".format(data, addr + 4*i))
datas.append(data)
if burst_length == 1:
return datas[0]
else:
return datas
def write(self, addr, data):
if isinstance(data, list):
burst_length = len(data)
else:
burst_length = 1
data = [data]
write_b(self.uart, self.cmds["write"])
write_b(self.uart, burst_length)
write_b(self.uart, (addr//4 & 0xff000000) >> 24)
write_b(self.uart, (addr//4 & 0x00ff0000) >> 16)
write_b(self.uart, (addr//4 & 0x0000ff00) >> 8)
write_b(self.uart, (addr//4 & 0x000000ff))
if isinstance(data, list):
for i in range(len(data)):
dat = data[i]
for j in range(4):
write_b(self.uart, (dat & 0xff000000) >> 24)
dat = dat << 8
if self.debug:
print("WR {:08X} @ {:08X}".format(data[i], (addr + i)*4))
else:
dat = data
word_addr = addr//4
write_b(self.uart, (word_addr >> 24) & 0xff)
write_b(self.uart, (word_addr >> 16) & 0xff)
write_b(self.uart, (word_addr >> 8) & 0xff)
write_b(self.uart, (word_addr >> 0) & 0xff)
for i in range(len(data)):
dat = data[i]
for j in range(4):
write_b(self.uart, (dat & 0xff000000) >> 24)
write_b(self.uart, (dat >> 24) & 0xff)
dat = dat << 8
if self.debug:
print("WR {:08X} @ {:08X}".format(data, (addr * 4)))
print("WR {:08X} @ {:08X}".format(data[i], addr + 4*i))