fifo: add support for depth=2

This commit is contained in:
Florent Kermarrec 2014-05-27 00:17:34 +02:00 committed by Sebastien Bourdeauducq
parent 70a2ee4368
commit 4c426b36f3

View file

@ -217,12 +217,16 @@ class AsyncFIFO(Module, _FIFOInterface):
NoRetiming(consume.q), NoRetiming(consume.q),
MultiReg(consume.q, consume_wdomain, "write") MultiReg(consume.q, consume_wdomain, "write")
] ]
self.comb += [ if depth_bits == 1:
self.writable.eq((produce.q[-1] == consume_wdomain[-1]) self.comb += self.writable.eq((produce.q[-1] == consume_wdomain[-1])
| (produce.q[-2] == consume_wdomain[-2]) | (produce.q[-2] == consume_wdomain[-2]))
| (produce.q[:-2] != consume_wdomain[:-2])), else:
self.readable.eq(consume.q != produce_rdomain) self.comb += [
] self.writable.eq((produce.q[-1] == consume_wdomain[-1])
| (produce.q[-2] == consume_wdomain[-2])
| (produce.q[:-2] != consume_wdomain[:-2]))
]
self.comb += self.readable.eq(consume.q != produce_rdomain)
storage = Memory(self.width, depth) storage = Memory(self.width, depth)
self.specials += storage self.specials += storage